OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.200.277 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$w?m]1@]1 Arial[* If the input goes beyond the absolute maximum range, the output will float to mid supply\* If the supply goes beyond the absolute maximum range, the output will float to mid supplySymbol????333333??;T_13793DC020200624144417;T_1379F42020200624144417;xxxxT_137A91D020200624144417;hxhxT_1372328020200624144417;8@8@T_1371A4E020200624144417; @ P @ PT_136F6C8020200624144417;T_136E8B4020200624144417;xxxxT_136C01C020200624144417;PPPPT_054A36B020200624144417;P8PXP8PXT_057F880020200624144417? hp hhpT_0570A76020200624144417;T_0571052020200624144417?  T_057108E020200624144417;T_0353497020200624144417;x@xPx@xPT_03534D3020200624144417;T_03523D5020200624144420:BHpU6T_0F710BF020200624143414 TLV4082TLV4082SC:\Users\a0227287\AppData\Local\Temp\DesignSoft\{Tina9-TI-01072020-103954}\TLV4082SCK#TLV4082LabelRC/X(d*IN1 @d*IN2>V(2)-1M),V(V ( @d*OUT1D 0 VALUE =  @ @d*OUT2 M @ @d*V+2DT   @d*V-1 8 @g"TLV4082Arial%333333?e@ddeGdde@HddU^l|@U^l|@* source TLV4082'* PSpice Model Editor - Version 16.6.0N*****************************************************************************J* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedH** or implied, with respect to this model, including the warranties of F** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality)** and performance is with the customer.N******************************************************************************D* This model is subject to change without notice. Texas Instruments:* Incorporated is not responsible for updating this model*N******************************************************************************'** Released by: Texas Instruments Inc.* Part: TLV4082* Date: 06/19/2020* Model Type: All In One* Simulator: PSPICE !* Simulator Version: 16.6.0.p001* EVM Order Number: N/A * EVM Users Guide: N/A "* Datasheet: SBVS404 - April 2020** Model Version: 1.0*N****************************************************************************** * Updates:*'* Version 1.0 : Release to Web *N***************************************************************************** * Notes:)* The following parameters are modeled: * Iq, tpd, Vcm, Vs, Vhys, Vol[* If the input goes beyond the absolute maximum range, the output will float to mid supply\* If the supply goes beyond the absolute maximum range, the output will float to mid supply*N******************************************************************************.SUBCKT TLV4082 IN1 IN2 OUT1 OUT2 V+ V- *X_U1 V- IN1 IN2 OUT1 OUT2 V+ SCHEMATIC1 .ENDS ..SUBCKT SCHEMATIC1 GND IN1 IN2 OUT1 OUT2 V+ .X_U1 V+ GND VDD_B VSS_B SUPPLY_BUFFER (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS$.SUBCKT Difference 1 2 OUT VDD VSS !EOUT OUT 0 VALUE = { V(1)- V(2)} R1 OUT 2 1 C1 2 0 1e-12.ENDS1.SUBCKT hpa_comphys INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }fEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) -1m ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS&.SUBCKT SUPPLY_BUFFER 1 2 VDD_B VSS_B EVDD_NEW VDD_B 0 VALUE = {V(1)} EVSS_NEW VSS_B 0 VALUE = {V(2)}.ENDS#.SUBCKT VCC_Range 1 2 OUT VDD VSS BEOUT OUT 0 VALUE = { IF( ( V(1) > V(2) - 1m ), V(VDD), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWRE1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) } R1 3 2 1 C1 2 0 1e-12.ENDS<.SUBCKT DIGLEVSHIFT_INV 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWRE1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VDD_NEW), V(VSS_NEW) ) } R1 3 2 1 C1 2 0 1e-12.ENDS.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS%.MODEL Qbreakn NPN(IS =1E-12,RC= 70)IN1IN2OUT1OUT2V+V-DBx V1T_0F715E3020200624143910Battery_9V_V (V)@BrxOUT1T_0F71875020200624143952 NOPCB (VF)BrOUT2T_0F718D3020200624143958 NOPCB (VF)DB  V2T_0554182020200624144037Battery_9V_V (V)$@Bp%IN1T_054B0DA020200624144310 Sgen (VG)9v??7AVB%IN2T_054B138020200624144318 Sgen (VG)9v??7AV B@R1T_054B1F4020200624144359R_AX600_W200 (R)@@?Y@ BR2T_054B196020200624144408R_AX600_W200 (R)@@?Y@Bnx VDDT_0F71585020200624143910 NOPCB (J)BnP8 VDDT_0F717B9020200624143939 NOPCB (J)Bn  VPUT_05540C6020200624144037 NOPCB (J)Bn8 VPUT_05541E0020200624144050 NOPCB (J)Bn VPUT_054AC14020200624144053 NOPCB (J)BfxPT_0F71527020200624143910 NOPCB (GND)BfT_0F71641020200624143915 NOPCB (GND)BfT_0F716FD020200624143931 NOPCB (GND)BfPT_0F71817020200624143944 NOPCB (GND)Bf PT_0554124020200624144037 NOPCB (GND)8?t ]@<"MbP??ư>'dd?Y@[dddd$@?.A.A.AeAMbP?@@?hUMu>ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname