OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.200.277 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved. $Circuit$0 I ?F[VF1]minx8=1 maxx8=1.07 divsx8=6 scalex8=0miny8=1 maxy8=1.5 divsy8=5 scaley8=0[Vout]minx1=1.994526627maxx1=2.002218935 divsx1=2 scalex1=0 minx8=2.4 maxx8=2.6 divsx8=4 scalex8=0[All] minx8=0.1 maxx8=3.3 divsx8=2 scalex8=0 minx1=0.0002 maxx1=0.0003 divsx1=2 scalex1=0[OUT+] minx8=2.22 maxx8=2.41 divsx8=8 scalex8=0miny1=1 maxy1=1.5 divsy1=1 scaley1=0[OUT-]miny1=1 maxy1=1.5 divsy1=1 scaley1=0[VM1] minx8=2.2 maxx8=2.43 divsx8=6 scalex8=0 [H_RSTn]miny1=0maxy1=4 divsy1=1 scaley1=0[M_INT]miny1=0maxy1=2 divsy1=1 scaley1=0 [H_LPWn]miny1=0maxy1=4 divsy1=1 scaley1=0jH@jH Arial  Host SideSymbol????333333??G4@G4 Arial LPWn/PRSn circuitSymbol????333333??yG@yG Arial  Module SideSymbol????333333??O@O Arial  ComparatorSymbol????333333??@ Arial  ComparatorSymbol????333333??@ Arial Level TranslatorSymbol????333333??N@N Arial Level TranslatorSymbol????333333??S/@S/ Arial INT/RSTn circuitSymbol????333333??@ Arial Open = InterruptLow = No InterruptSymbol????333333??J@J Arial Open = No Reset Low = ResetSymbol????333333??}@} Arial Level TranslatorSymbol????333333??O@O Arial High = High PowerOpen = Low PowerSymbol????333333???hhhhhT_0E89594020240228140811;T_0E8960C020240228140811;hxhxT_0E89648020240228140811?xxxxxT_0E89684020240228140811? x xxT_0E896C0020240228140811?T_0E89738020240228140811?xxxxT_0E89774020240228140811;0X0XT_0E89828020240228140811;PPT_0E898A0020240228140811?  T_0E898DC020240228140811;8hh8hhT_0E89918020240228140811;X8X8T_0E89954020240228140811;xxxxT_0E89990020240228140811;`p`pT_0E899CC020240228140811;(8(8T_0E89A08020240228140811; ` @ ` @T_0E89A44020240228140811;    T_0E89A80020240228140811;T_0E89AF8020240228140811;XxXxT_0E89B34020240228140811;T_0E89B70020240228140811; h hT_0E89BAC020240228140811;````T_0E89BE8020240228140811;`@`@T_0E89C24020240228140811;xxT_0E89C60020240228140811;xxT_0E89C9C020240228140811;T_0E89CD8020240228140811;T_0E89D14020240228140811;xxT_0E89D50020240228140811;T_0E89D8C020240228140811;XXXXT_0E89DC8020240228140811;XXXXT_0E89E04020240228140811;x(x8x(x8T_0E89E40020240228140811;x`xpx`xpT_0E89E7C020240228140811;T_0E89EB8020240228140811;T_0E89EF4020240228140811;88T_0E89F30020240228140811;0x0xT_0E89F6C020240228140811;T_0E89FA8020240228140811;ppT_0E89FE4020240228140811?@x@xxT_0E8A020020240228140811;(((8(((8T_0E8A05C020240228140811;(`(p(`(pT_0E8A098020240228140811;T_0E8A0D7020240228140811;T_0E8A113020240228140811?P0PP0T_0E8A14F020240228140811;T_0E8A18B020240228140811;T_0E8A1C7020240228140811;T_0E8A203020240228140811;T_0E8A23F020240228140811;T_0E8A27B020240228140811;T_0E8A2B7020240228140811;T_0E8A2F3020240228140811;T_0E8A41F020240228140811CPP  T_0E8A45B020240228140811;T_0E8A497020240228140811;T_0E8A4D3020240228140811;HhHhT_0E8A50F020240228140811?T_0E8A54B020240228140811;T_0B35A6F020240228140811?T_0B35AAB020240228140811;@@T_092F7AF020240228140811;T_0946286020240228140811;T_09462C2020240228140811;hhT_0977BC7020240228140833;hhhhT_09319C3020240228140847;hhhhT_0989EE9020240228140906?0h00hT_096240E020240228140911;T_09AD4BD020240228142632CPhP  hhT_09B5A30020240228142716DBX V1T_0C4E0BE020240227115909Battery_9V_V (V)ffffff @ BPR3T_0C4E002020240227115909R_AX600_W200 (R)@@@?Y@DB V5T_100B338020240227115909Battery_9V_V (V)?Bx8 M_INTT_100B27C020240227115910 Sgen (VG)??@& .> B@R1T_100B21E020240227115910R_AX600_W200 (R)@@?Y@B(8 H_RSTnT_100B104020240227115910 Sgen (VG)ffffff @,C6*?DB V2T_100B0A6020240227115910Battery_9V_V (V)@BtM_RSTnT_0409E15020240227120328 NOPCB (VF)Bw0F LPWn/PRSnT_043A0D7020240227120733 NOPCB (VF)B8 H_LPWnT_043A01B020240227120733 Sgen (VG)ffffff @,C6*?BtxH_PRSnT_0439F5F020240227120733 NOPCB (VF) BR13T_0439F01020240227120733R_AX600_W200 (R)@@?Y@ BR12T_0439EA3020240227120733R_AX600_W200 (R)L@@?Y@ B R11T_043A483020240227120733R_AX600_W200 (R)j@@?Y@:B4 U5T_043A425020240227120733 .SC:\Users\a0491820\AppData\Local\Temp\DesignSoft\{Tina9-TI-06162021-105733}\TLV7011U##xxd*In+XCF01SVO204p  @d*In-` @d*Out  @d*V+0<  @d*V-h/C  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?, @, @\ * TLV7011N*****************************************************************************M* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved. N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedG** or implied, with respect to this model, including the warranties ofF** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality(** and performance is with the customerN******************************************************************************D* This model is subject to change without notice. Texas Instruments;* Incorporated is not responsible for updating this model.*N******************************************************************************&* Released by: Texas Instruments Inc.* Part: TLV7011* Date: 07/14/2021* Model Type: TRANSIENT* Simulator: PSpice* Simulator Version: 17.4@* Datasheet: SLVSDM5F – SEPTEMBER 2017 – REVISED MARCH 2020*N****************************************************************************** * Updates:** Version 1.0 : Release to Web/* 2.0 : Improving Model Specifications*N***************************************************************************** * Notes:)* The following parameters are modeled: (* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhysb* If the input or supply rail goes beyond the abs max limits, the output will float at mid supply^* If one or both inputs go beyond the commmon mode limit, the output will float at mid supply.* Modeled based off of typical EC table specsN****************************************************************************** source TLV7011&.SUBCKT TLV7011 IN+ IN- OUT V+ V- X_U4 CMP N840186 Prop_Delay >X_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE PX_U5 N21237 INRANGE N786723 V+ V+_BUFFER V- V-_BUFFER N861676 OUT Output_Stage + /X_U6 V+ V+_BUFFER V- V-_BUFFER Supply_Buffer IX_U3 N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS I_IS N843683 V- DC 5u 8X_U7 N21237 N786723 V+_BUFFER V-_BUFFER Supply_Enable ,X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer I_IBP IN+ V- DC 5p I_IBN IN- V- DC 5p #V_VOS N785573 IN+BUFF 0.5m%R_RIS N843683 V+ 1u TC=0,0 &C_CINPL V- IN+ 0.5p TC=0,0 &C_CINNL V- IN- 0.5p TC=0,0 &C_CINPH IN+ V+ 0.5p TC=0,0 &C_CINNH IN- V+ 0.5p TC=0,0 V_VHYST N852568 0 4.2m%R_RS N857437 CMP 50 TC=0,0 2T_TPD N857437 0 N857443 0 Z0=50 TD=260n #R_RT 0 N857443 50 TC=0,0 ,X_S1 CMP 0 N858088 N840186 Top_Level_S1 ,X_S2 CMP 0 N858088 N857443 Top_Level_S2 3E_E1 N861676 V-_BUFFER N858088 V-_BUFFER 2.ENDS*$1.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS*$3.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER -X_U5 N16973 N20377 EN 1V 0 VCC_Range/X_U15 N20310 N16973 POR 1V 0 VCC_Range9X_U13 V+_BUFFER V-_BUFFER N16973 1V 0 Difference#V_VS_MIN_SET N20310 0 1.59#V_VS_MAX_SET N20377 0 5.51V_VLOGIC 1V 0 1.ENDS*$2.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS*$J.SUBCKT Output_Stage EN IN_RANGE POR V+ V+_BUFFER V- V-_BUFFER VIN VOUT 7X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID DX_U3 VIN N774212 V+_BUFFER V-_BUFFER V+ N774290 DIGLEVSHIFT0X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLYV_VLOGIC 1V 0 1V_V1 V+ N774290 1;X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ :X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE/X_U9 CONTROL_HIZ N789513 1V 0 INVERTER3X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE L_L1 N778484 VOUT 1n 'C_COUTH VOUT V+ 0.5p TC=0,0 'C_COUTL V- VOUT 0.5p TC=0,0 9X_SVOH N774212 N774290 N8491902 V+ Output_Stage_SVOH 8X_SVOL N774212 N774290 V- N850209 Output_Stage_SVOL -R_ROUTH N778496 N8491902 60 TC=0,0 ,R_ROUTL N850209 N778496 60 TC=0,0 .ENDS*$ 9.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER 'V_VCMNP N20415 V-_BUFFER -0.11&V_VCMPN N32066 V+_BUFFER 0.21@X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393&V_VCMPP N20155 V+_BUFFER 0.21'V_VCMNN N20539 V-_BUFFER -0.11AX_U21 N32066 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393AX_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393AX_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393OX_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE .ENDS*$.SUBCKT Prop_Delay VIN VOUT .T_TPD N03175 0 VOUT 0 Z0=50 TD=310n R_RT 0 VOUT 50 TC=0,0 $R_RS N03175 VIN 50 TC=0,0 .ENDS*$.subckt Top_Level_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G9.MODEL _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0 Von=1.ends Top_Level_S1*$.subckt Top_Level_S2 1 2 3 4 S_S2 3 4 1 2 _S2RS_S2 1 2 1G9.MODEL _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1 Von=0.ends Top_Level_S2*$$.subckt Output_Stage_SMID 1 2 3 4 S_SMID 3 4 1 2 _SMIDRS_SMID 1 2 1G<.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SMID*$$.subckt Output_Stage_SHIZ 1 2 3 4 S_SHIZ 3 4 1 2 _SHIZRS_SHIZ 1 2 1G<.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SHIZ*$$.subckt Output_Stage_SVOH 1 2 3 4 S_SVOH 3 4 1 2 _SVOHRS_SVOH 1 2 1G<.MODEL _SVOH VSWITCH Roff=1e12 Ron=1.0 Voff=0 Von=1.ends Output_Stage_SVOH*$$.subckt Output_Stage_SVOL 1 2 3 4 S_SVOL 3 4 1 2 _SVOLRS_SVOL 1 2 1G<.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SVOL*$.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS*$8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWS*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }:E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }* R1 3 2 1*C1 2 0 1e-12.ENDS*$&.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }=EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$.SUBCKT VIN_INV 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 2 0 1e-12.ENDS*$.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS*$.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS*$.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$!.SUBCKT NOR_GATE 1 2 OUT VDD VSSgEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 OUT 2 1C1 OUT 0 1e-12.ENDS*$'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS*$".SUBCKT PORCHECK 1 2 OUT VDD VSS =EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$$.SUBCKT Difference 1 2 OUT VDD VSS "EOUT OUT1 0 VALUE = { V(1)- V(2)}R1 OUT1 OUT 1*C1 OUT 0 1e-12.ENDS*$,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)}.ENDS*$#.SUBCKT VCC_Range 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }R1 OUT OUT2 1C1 OUT 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$1.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSSFEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}R1 OUT OUT2 1C1 OUT 0 1e-12 .ENDS*$8.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUTQEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}C1 OUT 0 1e-12.ENDS*$ .SUBCKT NORGATE 1 2 OUT VDD VSShEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$4.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$4.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$;.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT V_VLATCH N00729 V- 1.25)R_RPU N00729 LEHYST 40k TC=0,0 %E_EIN VLE V-_BUF LEHYST V- 1*R_R1 V-_BUF LATCH_OUT 1k TC=0,0 #R_R2 V-_BUF VLE 1k TC=0,0*R_R3 V-_BUF HYST_OUT 1k TC=0,0 AE_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }F*E_EHYST HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }5E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)+(0.5,0.0636)+(0.55,0.0636)+(0.6,0.0636)+(0.65,0.0636)+(0.7,0.0635)+(0.71,0.0636)+(0.72,0.0635)+(0.73,0.0636)+(0.74,0.0634)+(0.75,0.0635)+(0.76,0.0638)+(0.77,0.0637)+(0.78,0.0637)+(0.79,0.0637)+(0.8,0.0636)+(0.81,0.0636)+(0.82,0.0636)+(0.83,0.0636)+(0.84,0.0425)+(0.85,0.0411)+(0.86,0.0398)+(0.87,0.0386)+(0.88,0.0371)+(0.89,0.0359)+(0.9,0.0347)+(0.91,0.0334)+(0.92,0.032)+(0.93,0.0309)+(0.94,0.0296) +(1,0.0223)+(1.05,0.0164)+(1.1,0.0108)+(1.15,0.0056)+(1.2,0.0007) +(1.25,0).ENDS*$/.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBADcGIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }RIS VCC1 VCC 1*RIS2 VCC VEE 100000000.ENDS*$".SUBCKT 4ORGATE 1 2 3 4 5 VDD VSSE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 5 6 1.ENDS*$In+In-OutV+V-!B`SW1T_043A3C7020240227120733?eABt M_LPWnT_041698F020240227121110 NOPCB (VF) BR2T_0517364020240227130149R_AX600_W200 (R)@@?Y@DB V3T_0517130020240227134131Battery_9V_V (V)?:B]3 U3T_100B4B0020240227115910  SC:\Users\a0491820\AppData\Local\Temp\DesignSoft\{Tina9-TI-06162021-105733}\TLV7021TLV7021U##xxd*In+XCF01SVO204p  @d*In-` @d*Out  @d*V+0<  @d*V-h/C  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?4@4@T * TLV7011N*****************************************************************************M* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved. N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedG** or implied, with respect to this model, including the warranties ofF** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality(** and performance is with the customerN******************************************************************************D* This model is subject to change without notice. Texas Instruments;* Incorporated is not responsible for updating this model.*N******************************************************************************&* Released by: Texas Instruments Inc.* Part: TLV7011* Date: 07/14/2021* Model Type: TRANSIENT* Simulator: PSpice* Simulator Version: 17.4@* Datasheet: SLVSDM5F – SEPTEMBER 2017 – REVISED MARCH 2020*N****************************************************************************** * Updates:** Version 1.0 : Release to Web/* 2.0 : Improving Model Specifications*N***************************************************************************** * Notes:)* The following parameters are modeled: (* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhysb* If the input or supply rail goes beyond the abs max limits, the output will float at mid supply^* If one or both inputs go beyond the commmon mode limit, the output will float at mid supply.* Modeled based off of typical EC table specsN****************************************************************************** source TLV7021%.SUBCKT TLV7021 IN+ IN- V+ V- OUT X_U4 CMP N840186 Prop_Delay >X_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE PX_U5 N21237 INRANGE N786723 V+ V+_BUFFER V- V-_BUFFER N861676 OUT Output_Stage + /X_U6 V+ V+_BUFFER V- V-_BUFFER Supply_Buffer IX_U3 N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS I_IS N843683 V- DC 5u 8X_U7 N21237 N786723 V+_BUFFER V-_BUFFER Supply_Enable ,X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer I_IBP IN+ V- DC 5p I_IBN IN- V- DC 5p #V_VOS N785573 IN+BUFF 0.5m%R_RIS N843683 V+ 1u TC=0,0 &C_CINPL V- IN+ 0.5p TC=0,0 &C_CINNL V- IN- 0.5p TC=0,0 &C_CINPH IN+ V+ 0.5p TC=0,0 &C_CINNH IN- V+ 0.5p TC=0,0 V_VHYST N852568 0 4.2m%R_RS N857437 CMP 50 TC=0,0 2T_TPD N857437 0 N857443 0 Z0=50 TD=260n #R_RT 0 N857443 50 TC=0,0 ,X_S1 CMP 0 N858088 N840186 Top_Level_S1 ,X_S2 CMP 0 N858088 N857443 Top_Level_S2 3E_E1 N861676 V-_BUFFER N858088 V-_BUFFER 2.ENDS*$1.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS*$3.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER -X_U5 N16973 N20377 EN 1V 0 VCC_Range/X_U15 N20310 N16973 POR 1V 0 VCC_Range9X_U13 V+_BUFFER V-_BUFFER N16973 1V 0 Difference#V_VS_MIN_SET N20310 0 1.59#V_VS_MAX_SET N20377 0 5.51V_VLOGIC 1V 0 1.ENDS*$2.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS*$J.SUBCKT Output_Stage EN IN_RANGE POR V+ V+_BUFFER V- V-_BUFFER VIN VOUT 7X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID DX_U3 VIN N774212 V+_BUFFER V-_BUFFER V+ N774290 DIGLEVSHIFT0X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLYV_VLOGIC 1V 0 1V_V1 V+ N774290 1;X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ :X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE/X_U9 CONTROL_HIZ N789513 1V 0 INVERTER3X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE L_L1 N778484 VOUT 1n 'C_COUTH VOUT V+ 0.5p TC=0,0 'C_COUTL V- VOUT 0.5p TC=0,0 8X_SVOL N774212 N774290 V- N850209 Output_Stage_SVOL ,R_ROUTL N850209 N778496 60 TC=0,0 .ENDS*$9.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER 'V_VCMNP N20415 V-_BUFFER -0.11&V_VCMPN N32066 V+_BUFFER 0.21@X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393&V_VCMPP N20155 V+_BUFFER 0.21'V_VCMNN N20539 V-_BUFFER -0.11AX_U21 N32066 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393AX_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393AX_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393OX_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE .ENDS*$ .SUBCKT Prop_Delay VIN VOUT .T_TPD N03175 0 VOUT 0 Z0=50 TD=310n R_RT 0 VOUT 50 TC=0,0 $R_RS N03175 VIN 50 TC=0,0 .ENDS*$.subckt Top_Level_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G9.MODEL _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0 Von=1.ends Top_Level_S1*$.subckt Top_Level_S2 1 2 3 4 S_S2 3 4 1 2 _S2RS_S2 1 2 1G9.MODEL _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1 Von=0.ends Top_Level_S2*$$.subckt Output_Stage_SMID 1 2 3 4 S_SMID 3 4 1 2 _SMIDRS_SMID 1 2 1G<.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SMID*$$.subckt Output_Stage_SHIZ 1 2 3 4 S_SHIZ 3 4 1 2 _SHIZRS_SHIZ 1 2 1G<.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SHIZ*$$.subckt Output_Stage_SVOL 1 2 3 4 S_SVOL 3 4 1 2 _SVOLRS_SVOL 1 2 1G<.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SVOL*$.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS*$8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWS*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }:E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }* R1 3 2 1*C1 2 0 1e-12.ENDS*$&.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }=EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$.SUBCKT VIN_INV 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 2 0 1e-12.ENDS*$.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS*$.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS*$.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$!.SUBCKT NOR_GATE 1 2 OUT VDD VSSgEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 OUT 2 1C1 OUT 0 1e-12.ENDS*$'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS*$".SUBCKT PORCHECK 1 2 OUT VDD VSS =EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$$.SUBCKT Difference 1 2 OUT VDD VSS "EOUT OUT1 0 VALUE = { V(1)- V(2)}R1 OUT1 OUT 1*C1 OUT 0 1e-12.ENDS*$,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)}.ENDS*$#.SUBCKT VCC_Range 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }R1 OUT OUT2 1C1 OUT 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$1.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSSFEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}R1 OUT OUT2 1C1 OUT 0 1e-12 .ENDS*$8.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUTQEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}C1 OUT 0 1e-12.ENDS*$ .SUBCKT NORGATE 1 2 OUT VDD VSShEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$4.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$4.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$;.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT V_VLATCH N00729 V- 1.25)R_RPU N00729 LEHYST 40k TC=0,0 %E_EIN VLE V-_BUF LEHYST V- 1*R_R1 V-_BUF LATCH_OUT 1k TC=0,0 #R_R2 V-_BUF VLE 1k TC=0,0*R_R3 V-_BUF HYST_OUT 1k TC=0,0 AE_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }F*E_EHYST HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }5E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)+(0.5,0.0636)+(0.55,0.0636)+(0.6,0.0636)+(0.65,0.0636)+(0.7,0.0635)+(0.71,0.0636)+(0.72,0.0635)+(0.73,0.0636)+(0.74,0.0634)+(0.75,0.0635)+(0.76,0.0638)+(0.77,0.0637)+(0.78,0.0637)+(0.79,0.0637)+(0.8,0.0636)+(0.81,0.0636)+(0.82,0.0636)+(0.83,0.0636)+(0.84,0.0425)+(0.85,0.0411)+(0.86,0.0398)+(0.87,0.0386)+(0.88,0.0371)+(0.89,0.0359)+(0.9,0.0347)+(0.91,0.0334)+(0.92,0.032)+(0.93,0.0309)+(0.94,0.0296) +(1,0.0223)+(1.05,0.0164)+(1.1,0.0108)+(1.15,0.0056)+(1.2,0.0007) +(1.25,0).ENDS*$/.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBADcGIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }RIS VCC1 VCC 1*RIS2 VCC VEE 100000000.ENDS*$".SUBCKT 4ORGATE 1 2 3 4 5 VDD VSSE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 5 6 1.ENDS*$In+In-V+V-Out:B4x#U6T_043A079020240227120733  SC:\Users\a0491820\AppData\Local\Temp\DesignSoft\{Tina9-TI-06162021-105733}\TLV7011TLV7011U##xxd*In+XCF01SVO204p  @d*In-` @d*Out  @d*V+0<  @d*V-h/C  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?, @, @\ * TLV7011N*****************************************************************************M* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved. N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedG** or implied, with respect to this model, including the warranties ofF** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality(** and performance is with the customerN******************************************************************************D* This model is subject to change without notice. Texas Instruments;* Incorporated is not responsible for updating this model.*N******************************************************************************&* Released by: Texas Instruments Inc.* Part: TLV7011* Date: 07/14/2021* Model Type: TRANSIENT* Simulator: PSpice* Simulator Version: 17.4@* Datasheet: SLVSDM5F – SEPTEMBER 2017 – REVISED MARCH 2020*N****************************************************************************** * Updates:** Version 1.0 : Release to Web/* 2.0 : Improving Model Specifications*N***************************************************************************** * Notes:)* The following parameters are modeled: (* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhysb* If the input or supply rail goes beyond the abs max limits, the output will float at mid supply^* If one or both inputs go beyond the commmon mode limit, the output will float at mid supply.* Modeled based off of typical EC table specsN****************************************************************************** source TLV7011&.SUBCKT TLV7011 IN+ IN- OUT V+ V- X_U4 CMP N840186 Prop_Delay >X_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE PX_U5 N21237 INRANGE N786723 V+ V+_BUFFER V- V-_BUFFER N861676 OUT Output_Stage + /X_U6 V+ V+_BUFFER V- V-_BUFFER Supply_Buffer IX_U3 N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS I_IS N843683 V- DC 5u 8X_U7 N21237 N786723 V+_BUFFER V-_BUFFER Supply_Enable ,X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer I_IBP IN+ V- DC 5p I_IBN IN- V- DC 5p #V_VOS N785573 IN+BUFF 0.5m%R_RIS N843683 V+ 1u TC=0,0 &C_CINPL V- IN+ 0.5p TC=0,0 &C_CINNL V- IN- 0.5p TC=0,0 &C_CINPH IN+ V+ 0.5p TC=0,0 &C_CINNH IN- V+ 0.5p TC=0,0 V_VHYST N852568 0 4.2m%R_RS N857437 CMP 50 TC=0,0 2T_TPD N857437 0 N857443 0 Z0=50 TD=260n #R_RT 0 N857443 50 TC=0,0 ,X_S1 CMP 0 N858088 N840186 Top_Level_S1 ,X_S2 CMP 0 N858088 N857443 Top_Level_S2 3E_E1 N861676 V-_BUFFER N858088 V-_BUFFER 2.ENDS*$1.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS*$3.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER -X_U5 N16973 N20377 EN 1V 0 VCC_Range/X_U15 N20310 N16973 POR 1V 0 VCC_Range9X_U13 V+_BUFFER V-_BUFFER N16973 1V 0 Difference#V_VS_MIN_SET N20310 0 1.59#V_VS_MAX_SET N20377 0 5.51V_VLOGIC 1V 0 1.ENDS*$2.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS*$J.SUBCKT Output_Stage EN IN_RANGE POR V+ V+_BUFFER V- V-_BUFFER VIN VOUT 7X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID DX_U3 VIN N774212 V+_BUFFER V-_BUFFER V+ N774290 DIGLEVSHIFT0X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLYV_VLOGIC 1V 0 1V_V1 V+ N774290 1;X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ :X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE/X_U9 CONTROL_HIZ N789513 1V 0 INVERTER3X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE L_L1 N778484 VOUT 1n 'C_COUTH VOUT V+ 0.5p TC=0,0 'C_COUTL V- VOUT 0.5p TC=0,0 9X_SVOH N774212 N774290 N8491902 V+ Output_Stage_SVOH 8X_SVOL N774212 N774290 V- N850209 Output_Stage_SVOL -R_ROUTH N778496 N8491902 60 TC=0,0 ,R_ROUTL N850209 N778496 60 TC=0,0 .ENDS*$ 9.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER 'V_VCMNP N20415 V-_BUFFER -0.11&V_VCMPN N32066 V+_BUFFER 0.21@X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393&V_VCMPP N20155 V+_BUFFER 0.21'V_VCMNN N20539 V-_BUFFER -0.11AX_U21 N32066 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393AX_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393AX_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393OX_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE .ENDS*$.SUBCKT Prop_Delay VIN VOUT .T_TPD N03175 0 VOUT 0 Z0=50 TD=310n R_RT 0 VOUT 50 TC=0,0 $R_RS N03175 VIN 50 TC=0,0 .ENDS*$.subckt Top_Level_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G9.MODEL _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0 Von=1.ends Top_Level_S1*$.subckt Top_Level_S2 1 2 3 4 S_S2 3 4 1 2 _S2RS_S2 1 2 1G9.MODEL _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1 Von=0.ends Top_Level_S2*$$.subckt Output_Stage_SMID 1 2 3 4 S_SMID 3 4 1 2 _SMIDRS_SMID 1 2 1G<.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SMID*$$.subckt Output_Stage_SHIZ 1 2 3 4 S_SHIZ 3 4 1 2 _SHIZRS_SHIZ 1 2 1G<.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SHIZ*$$.subckt Output_Stage_SVOH 1 2 3 4 S_SVOH 3 4 1 2 _SVOHRS_SVOH 1 2 1G<.MODEL _SVOH VSWITCH Roff=1e12 Ron=1.0 Voff=0 Von=1.ends Output_Stage_SVOH*$$.subckt Output_Stage_SVOL 1 2 3 4 S_SVOL 3 4 1 2 _SVOLRS_SVOL 1 2 1G<.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SVOL*$.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS*$8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWS*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }:E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }* R1 3 2 1*C1 2 0 1e-12.ENDS*$&.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }=EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$.SUBCKT VIN_INV 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 2 0 1e-12.ENDS*$.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS*$.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS*$.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$!.SUBCKT NOR_GATE 1 2 OUT VDD VSSgEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 OUT 2 1C1 OUT 0 1e-12.ENDS*$'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS*$".SUBCKT PORCHECK 1 2 OUT VDD VSS =EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$$.SUBCKT Difference 1 2 OUT VDD VSS "EOUT OUT1 0 VALUE = { V(1)- V(2)}R1 OUT1 OUT 1*C1 OUT 0 1e-12.ENDS*$,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)}.ENDS*$#.SUBCKT VCC_Range 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }R1 OUT OUT2 1C1 OUT 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$1.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSSFEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}R1 OUT OUT2 1C1 OUT 0 1e-12 .ENDS*$8.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUTQEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}C1 OUT 0 1e-12.ENDS*$ .SUBCKT NORGATE 1 2 OUT VDD VSShEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$4.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$4.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$;.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT V_VLATCH N00729 V- 1.25)R_RPU N00729 LEHYST 40k TC=0,0 %E_EIN VLE V-_BUF LEHYST V- 1*R_R1 V-_BUF LATCH_OUT 1k TC=0,0 #R_R2 V-_BUF VLE 1k TC=0,0*R_R3 V-_BUF HYST_OUT 1k TC=0,0 AE_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }F*E_EHYST HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }5E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)+(0.5,0.0636)+(0.55,0.0636)+(0.6,0.0636)+(0.65,0.0636)+(0.7,0.0635)+(0.71,0.0636)+(0.72,0.0635)+(0.73,0.0636)+(0.74,0.0634)+(0.75,0.0635)+(0.76,0.0638)+(0.77,0.0637)+(0.78,0.0637)+(0.79,0.0637)+(0.8,0.0636)+(0.81,0.0636)+(0.82,0.0636)+(0.83,0.0636)+(0.84,0.0425)+(0.85,0.0411)+(0.86,0.0398)+(0.87,0.0386)+(0.88,0.0371)+(0.89,0.0359)+(0.9,0.0347)+(0.91,0.0334)+(0.92,0.032)+(0.93,0.0309)+(0.94,0.0296) +(1,0.0223)+(1.05,0.0164)+(1.1,0.0108)+(1.15,0.0056)+(1.2,0.0007) +(1.25,0).ENDS*$/.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBADcGIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }RIS VCC1 VCC 1*RIS2 VCC VEE 100000000.ENDS*$".SUBCKT 4ORGATE 1 2 3 4 5 VDD VSSE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 5 6 1.ENDS*$In+In-OutV+V-:B]3U4T_100B50E020240227115910  SC:\Users\a0491820\AppData\Local\Temp\DesignSoft\{Tina9-TI-06162021-105733}\TLV7021TLV7021U##xxd*In+XCF01SVO204p  @d*In-` @d*Out  @d*V+0<  @d*V-h/C  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?4@4@T * TLV7011N*****************************************************************************M* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved. N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedG** or implied, with respect to this model, including the warranties ofF** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality(** and performance is with the customerN******************************************************************************D* This model is subject to change without notice. Texas Instruments;* Incorporated is not responsible for updating this model.*N******************************************************************************&* Released by: Texas Instruments Inc.* Part: TLV7011* Date: 07/14/2021* Model Type: TRANSIENT* Simulator: PSpice* Simulator Version: 17.4@* Datasheet: SLVSDM5F – SEPTEMBER 2017 – REVISED MARCH 2020*N****************************************************************************** * Updates:** Version 1.0 : Release to Web/* 2.0 : Improving Model Specifications*N***************************************************************************** * Notes:)* The following parameters are modeled: (* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhysb* If the input or supply rail goes beyond the abs max limits, the output will float at mid supply^* If one or both inputs go beyond the commmon mode limit, the output will float at mid supply.* Modeled based off of typical EC table specsN****************************************************************************** source TLV7021%.SUBCKT TLV7021 IN+ IN- V+ V- OUT X_U4 CMP N840186 Prop_Delay >X_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE PX_U5 N21237 INRANGE N786723 V+ V+_BUFFER V- V-_BUFFER N861676 OUT Output_Stage + /X_U6 V+ V+_BUFFER V- V-_BUFFER Supply_Buffer IX_U3 N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS I_IS N843683 V- DC 5u 8X_U7 N21237 N786723 V+_BUFFER V-_BUFFER Supply_Enable ,X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer I_IBP IN+ V- DC 5p I_IBN IN- V- DC 5p #V_VOS N785573 IN+BUFF 0.5m%R_RIS N843683 V+ 1u TC=0,0 &C_CINPL V- IN+ 0.5p TC=0,0 &C_CINNL V- IN- 0.5p TC=0,0 &C_CINPH IN+ V+ 0.5p TC=0,0 &C_CINNH IN- V+ 0.5p TC=0,0 V_VHYST N852568 0 4.2m%R_RS N857437 CMP 50 TC=0,0 2T_TPD N857437 0 N857443 0 Z0=50 TD=260n #R_RT 0 N857443 50 TC=0,0 ,X_S1 CMP 0 N858088 N840186 Top_Level_S1 ,X_S2 CMP 0 N858088 N857443 Top_Level_S2 3E_E1 N861676 V-_BUFFER N858088 V-_BUFFER 2.ENDS*$1.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS*$3.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER -X_U5 N16973 N20377 EN 1V 0 VCC_Range/X_U15 N20310 N16973 POR 1V 0 VCC_Range9X_U13 V+_BUFFER V-_BUFFER N16973 1V 0 Difference#V_VS_MIN_SET N20310 0 1.59#V_VS_MAX_SET N20377 0 5.51V_VLOGIC 1V 0 1.ENDS*$2.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS*$J.SUBCKT Output_Stage EN IN_RANGE POR V+ V+_BUFFER V- V-_BUFFER VIN VOUT 7X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID DX_U3 VIN N774212 V+_BUFFER V-_BUFFER V+ N774290 DIGLEVSHIFT0X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLYV_VLOGIC 1V 0 1V_V1 V+ N774290 1;X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ :X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE/X_U9 CONTROL_HIZ N789513 1V 0 INVERTER3X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE L_L1 N778484 VOUT 1n 'C_COUTH VOUT V+ 0.5p TC=0,0 'C_COUTL V- VOUT 0.5p TC=0,0 8X_SVOL N774212 N774290 V- N850209 Output_Stage_SVOL ,R_ROUTL N850209 N778496 60 TC=0,0 .ENDS*$9.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER 'V_VCMNP N20415 V-_BUFFER -0.11&V_VCMPN N32066 V+_BUFFER 0.21@X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393&V_VCMPP N20155 V+_BUFFER 0.21'V_VCMNN N20539 V-_BUFFER -0.11AX_U21 N32066 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393AX_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393AX_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393OX_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE .ENDS*$ .SUBCKT Prop_Delay VIN VOUT .T_TPD N03175 0 VOUT 0 Z0=50 TD=310n R_RT 0 VOUT 50 TC=0,0 $R_RS N03175 VIN 50 TC=0,0 .ENDS*$.subckt Top_Level_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G9.MODEL _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0 Von=1.ends Top_Level_S1*$.subckt Top_Level_S2 1 2 3 4 S_S2 3 4 1 2 _S2RS_S2 1 2 1G9.MODEL _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1 Von=0.ends Top_Level_S2*$$.subckt Output_Stage_SMID 1 2 3 4 S_SMID 3 4 1 2 _SMIDRS_SMID 1 2 1G<.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SMID*$$.subckt Output_Stage_SHIZ 1 2 3 4 S_SHIZ 3 4 1 2 _SHIZRS_SHIZ 1 2 1G<.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SHIZ*$$.subckt Output_Stage_SVOL 1 2 3 4 S_SVOL 3 4 1 2 _SVOLRS_SVOL 1 2 1G<.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SVOL*$.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS*$8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWS*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }:E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }* R1 3 2 1*C1 2 0 1e-12.ENDS*$&.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }=EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$.SUBCKT VIN_INV 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 2 0 1e-12.ENDS*$.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS*$.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS*$.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$!.SUBCKT NOR_GATE 1 2 OUT VDD VSSgEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 OUT 2 1C1 OUT 0 1e-12.ENDS*$'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS*$".SUBCKT PORCHECK 1 2 OUT VDD VSS =EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$$.SUBCKT Difference 1 2 OUT VDD VSS "EOUT OUT1 0 VALUE = { V(1)- V(2)}R1 OUT1 OUT 1*C1 OUT 0 1e-12.ENDS*$,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)}.ENDS*$#.SUBCKT VCC_Range 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }R1 OUT OUT2 1C1 OUT 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$1.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSSFEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}R1 OUT OUT2 1C1 OUT 0 1e-12 .ENDS*$8.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUTQEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}C1 OUT 0 1e-12.ENDS*$ .SUBCKT NORGATE 1 2 OUT VDD VSShEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$4.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$4.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$;.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT V_VLATCH N00729 V- 1.25)R_RPU N00729 LEHYST 40k TC=0,0 %E_EIN VLE V-_BUF LEHYST V- 1*R_R1 V-_BUF LATCH_OUT 1k TC=0,0 #R_R2 V-_BUF VLE 1k TC=0,0*R_R3 V-_BUF HYST_OUT 1k TC=0,0 AE_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }F*E_EHYST HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }5E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)+(0.5,0.0636)+(0.55,0.0636)+(0.6,0.0636)+(0.65,0.0636)+(0.7,0.0635)+(0.71,0.0636)+(0.72,0.0635)+(0.73,0.0636)+(0.74,0.0634)+(0.75,0.0635)+(0.76,0.0638)+(0.77,0.0637)+(0.78,0.0637)+(0.79,0.0637)+(0.8,0.0636)+(0.81,0.0636)+(0.82,0.0636)+(0.83,0.0636)+(0.84,0.0425)+(0.85,0.0411)+(0.86,0.0398)+(0.87,0.0386)+(0.88,0.0371)+(0.89,0.0359)+(0.9,0.0347)+(0.91,0.0334)+(0.92,0.032)+(0.93,0.0309)+(0.94,0.0296) +(1,0.0223)+(1.05,0.0164)+(1.1,0.0108)+(1.15,0.0056)+(1.2,0.0007) +(1.25,0).ENDS*$/.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBADcGIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }RIS VCC1 VCC 1*RIS2 VCC VEE 100000000.ENDS*$".SUBCKT 4ORGATE 1 2 3 4 5 VDD VSSE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 5 6 1.ENDS*$In+In-V+V-Out:B4 U2T_100B162020240227115910  SC:\Users\a0491820\AppData\Local\Temp\DesignSoft\{Tina9-TI-06162021-105733}\TLV7011TLV7011U##xxd*In+XCF01SVO204p  @d*In-` @d*Out  @d*V+0<  @d*V-h/C  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?, @, @\ * TLV7011N*****************************************************************************M* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved. N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedG** or implied, with respect to this model, including the warranties ofF** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality(** and performance is with the customerN******************************************************************************D* This model is subject to change without notice. Texas Instruments;* Incorporated is not responsible for updating this model.*N******************************************************************************&* Released by: Texas Instruments Inc.* Part: TLV7011* Date: 07/14/2021* Model Type: TRANSIENT* Simulator: PSpice* Simulator Version: 17.4@* Datasheet: SLVSDM5F – SEPTEMBER 2017 – REVISED MARCH 2020*N****************************************************************************** * Updates:** Version 1.0 : Release to Web/* 2.0 : Improving Model Specifications*N***************************************************************************** * Notes:)* The following parameters are modeled: (* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhysb* If the input or supply rail goes beyond the abs max limits, the output will float at mid supply^* If one or both inputs go beyond the commmon mode limit, the output will float at mid supply.* Modeled based off of typical EC table specsN****************************************************************************** source TLV7011&.SUBCKT TLV7011 IN+ IN- OUT V+ V- X_U4 CMP N840186 Prop_Delay >X_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE PX_U5 N21237 INRANGE N786723 V+ V+_BUFFER V- V-_BUFFER N861676 OUT Output_Stage + /X_U6 V+ V+_BUFFER V- V-_BUFFER Supply_Buffer IX_U3 N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS I_IS N843683 V- DC 5u 8X_U7 N21237 N786723 V+_BUFFER V-_BUFFER Supply_Enable ,X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer I_IBP IN+ V- DC 5p I_IBN IN- V- DC 5p #V_VOS N785573 IN+BUFF 0.5m%R_RIS N843683 V+ 1u TC=0,0 &C_CINPL V- IN+ 0.5p TC=0,0 &C_CINNL V- IN- 0.5p TC=0,0 &C_CINPH IN+ V+ 0.5p TC=0,0 &C_CINNH IN- V+ 0.5p TC=0,0 V_VHYST N852568 0 4.2m%R_RS N857437 CMP 50 TC=0,0 2T_TPD N857437 0 N857443 0 Z0=50 TD=260n #R_RT 0 N857443 50 TC=0,0 ,X_S1 CMP 0 N858088 N840186 Top_Level_S1 ,X_S2 CMP 0 N858088 N857443 Top_Level_S2 3E_E1 N861676 V-_BUFFER N858088 V-_BUFFER 2.ENDS*$1.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS*$3.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER -X_U5 N16973 N20377 EN 1V 0 VCC_Range/X_U15 N20310 N16973 POR 1V 0 VCC_Range9X_U13 V+_BUFFER V-_BUFFER N16973 1V 0 Difference#V_VS_MIN_SET N20310 0 1.59#V_VS_MAX_SET N20377 0 5.51V_VLOGIC 1V 0 1.ENDS*$2.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS*$J.SUBCKT Output_Stage EN IN_RANGE POR V+ V+_BUFFER V- V-_BUFFER VIN VOUT 7X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID DX_U3 VIN N774212 V+_BUFFER V-_BUFFER V+ N774290 DIGLEVSHIFT0X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLYV_VLOGIC 1V 0 1V_V1 V+ N774290 1;X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ :X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE/X_U9 CONTROL_HIZ N789513 1V 0 INVERTER3X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE L_L1 N778484 VOUT 1n 'C_COUTH VOUT V+ 0.5p TC=0,0 'C_COUTL V- VOUT 0.5p TC=0,0 9X_SVOH N774212 N774290 N8491902 V+ Output_Stage_SVOH 8X_SVOL N774212 N774290 V- N850209 Output_Stage_SVOL -R_ROUTH N778496 N8491902 60 TC=0,0 ,R_ROUTL N850209 N778496 60 TC=0,0 .ENDS*$ 9.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER 'V_VCMNP N20415 V-_BUFFER -0.11&V_VCMPN N32066 V+_BUFFER 0.21@X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393&V_VCMPP N20155 V+_BUFFER 0.21'V_VCMNN N20539 V-_BUFFER -0.11AX_U21 N32066 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393AX_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393AX_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393OX_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE .ENDS*$.SUBCKT Prop_Delay VIN VOUT .T_TPD N03175 0 VOUT 0 Z0=50 TD=310n R_RT 0 VOUT 50 TC=0,0 $R_RS N03175 VIN 50 TC=0,0 .ENDS*$.subckt Top_Level_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G9.MODEL _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0 Von=1.ends Top_Level_S1*$.subckt Top_Level_S2 1 2 3 4 S_S2 3 4 1 2 _S2RS_S2 1 2 1G9.MODEL _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1 Von=0.ends Top_Level_S2*$$.subckt Output_Stage_SMID 1 2 3 4 S_SMID 3 4 1 2 _SMIDRS_SMID 1 2 1G<.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SMID*$$.subckt Output_Stage_SHIZ 1 2 3 4 S_SHIZ 3 4 1 2 _SHIZRS_SHIZ 1 2 1G<.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SHIZ*$$.subckt Output_Stage_SVOH 1 2 3 4 S_SVOH 3 4 1 2 _SVOHRS_SVOH 1 2 1G<.MODEL _SVOH VSWITCH Roff=1e12 Ron=1.0 Voff=0 Von=1.ends Output_Stage_SVOH*$$.subckt Output_Stage_SVOL 1 2 3 4 S_SVOL 3 4 1 2 _SVOLRS_SVOL 1 2 1G<.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SVOL*$.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS*$8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWS*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }:E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }* R1 3 2 1*C1 2 0 1e-12.ENDS*$&.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }=EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$%.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }AEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$.SUBCKT VIN_INV 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 2 0 1e-12.ENDS*$.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS*$.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS*$.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$!.SUBCKT NOR_GATE 1 2 OUT VDD VSSgEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 OUT 2 1C1 OUT 0 1e-12.ENDS*$'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS*$".SUBCKT PORCHECK 1 2 OUT VDD VSS =EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$$.SUBCKT Difference 1 2 OUT VDD VSS "EOUT OUT1 0 VALUE = { V(1)- V(2)}R1 OUT1 OUT 1*C1 OUT 0 1e-12.ENDS*$,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)}.ENDS*$#.SUBCKT VCC_Range 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }R1 OUT OUT2 1C1 OUT 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$1.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSSFEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}R1 OUT OUT2 1C1 OUT 0 1e-12 .ENDS*$8.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUTQEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}C1 OUT 0 1e-12.ENDS*$ .SUBCKT NORGATE 1 2 OUT VDD VSShEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$4.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$4.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n *$;.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT V_VLATCH N00729 V- 1.25)R_RPU N00729 LEHYST 40k TC=0,0 %E_EIN VLE V-_BUF LEHYST V- 1*R_R1 V-_BUF LATCH_OUT 1k TC=0,0 #R_R2 V-_BUF VLE 1k TC=0,0*R_R3 V-_BUF HYST_OUT 1k TC=0,0 AE_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }F*E_EHYST HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }5E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)+(0.5,0.0636)+(0.55,0.0636)+(0.6,0.0636)+(0.65,0.0636)+(0.7,0.0635)+(0.71,0.0636)+(0.72,0.0635)+(0.73,0.0636)+(0.74,0.0634)+(0.75,0.0635)+(0.76,0.0638)+(0.77,0.0637)+(0.78,0.0637)+(0.79,0.0637)+(0.8,0.0636)+(0.81,0.0636)+(0.82,0.0636)+(0.83,0.0636)+(0.84,0.0425)+(0.85,0.0411)+(0.86,0.0398)+(0.87,0.0386)+(0.88,0.0371)+(0.89,0.0359)+(0.9,0.0347)+(0.91,0.0334)+(0.92,0.032)+(0.93,0.0309)+(0.94,0.0296) +(1,0.0223)+(1.05,0.0164)+(1.1,0.0108)+(1.15,0.0056)+(1.2,0.0007) +(1.25,0).ENDS*$/.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBADcGIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }RIS VCC1 VCC 1*RIS2 VCC VEE 100000000.ENDS*$".SUBCKT 4ORGATE 1 2 3 4 5 VDD VSSE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 5 6 1.ENDS*$In+In-OutV+V-:B U1T_1CF4B11020240227144610  TLV4062SC:\Users\a0488729\AppData\Local\Temp\DesignSoft\{Tina9-TI-06252021-095111}\TLV4062TLV4062TLV4062LabelMQJPX(d*IN12-  @d*IN21 ( @d*OUT1D L  0 @d*OUT2D 0 VALUE =  0  @d*V+2>=V(2)),V(VDD  @d*V-1>=V(2)),V(VSS @ @g"TLV4062Arial-333333?eNdde7ddeN7dd*$@*$@* source TLV4062).SUBCKT TLV4062 IN1 IN2 V+ V- OUT1 OUT2 !X_U4 N21103 N856401 Prop_Delay 6X_U2 IN2 IN1 INRANGE V+_BUFFER V-_BUFFER INPUTRANGE HX_U5 EN INRANGE 0 V+ V+_BUFFER V- V-_BUFFER N856405 OUT1 Output_Stage /X_U6 V+ V+_BUFFER V- V-_BUFFER Supply_Buffer KX_U3 N859229 N21074 N21103 V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS#I_IS N843683 V- DC 2.09u .X_U7 EN 0 V+_BUFFER V-_BUFFER Supply_Enable ,X_U1 IN1 N859221 IN1- N21074 Input_Buffer %R_RIS N843683 V+ 1u TC=0,0 &C_CINPL V- IN+ 0.5p TC=0,0 &C_CINNL V- IN- 0.5p TC=0,0 &C_CINPH IN+ V+ 0.5p TC=0,0 &C_CINNH IN- V+ 0.5p TC=0,0 V_VHYST N852568 0 30m3E_E1 N856405 V-_BUFFER N856401 V-_BUFFER 2V_VREF2 IN1- V- 1.164 V_VOS N859229 N859221 0.X_DESD5 V- IN- DESD PARAMS: AREA=1.0.X_DESD3 V- IN+ DESD PARAMS: AREA=1.0I_IBP2 IN1 V- DC 1n #X_U11 N868679 N868685 Prop_Delay V_VREF3 IN2- V- 1.164MX_U9 N868475 N868713 N868679 V+_BUFFER V-_BUFFER N868751 HPA_COMPHYS!V_VOS1 N868475 N868467 0V_VHYST1 N868751 0 30m3E_E2 N868691 V-_BUFFER N868685 V-_BUFFER 2I_IBP3 IN2 V- DC 1n .X_U10 IN2 N868467 IN2- N868713 Input_Buffer IX_U12 EN INRANGE 0 V+ V+_BUFFER V- V-_BUFFER N868691 OUT2 Output_Stage .ENDS 1.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS 3.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER $V_VS_MAX_SET N786149 0 5.51V_VLOGIC 1V 0 1:X_U13 V+_BUFFER V-_BUFFER N786239 1V 0 Difference4X_U5 N786239 N786149 N786253 1V 0 VCC_Range.X_U17 N786253 N786357 EN 1V 0 ORGATE %V_VS_MIN_SET1 N786471 0 1.49$V_VS_MIN_SET N786643 0 1.495X_U16 N786471 N786239 N786357 1V 0 VCC_Range1X_U15 N786643 N786239 POR 1V 0 VCC_Range.ENDS 2.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS J.SUBCKT Output_Stage EN IN_RANGE POR V+ V+_BUFFER V- V-_BUFFER VIN VOUT 7X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID DX_U3 VIN N774212 V+_BUFFER V-_BUFFER V+ N774290 DIGLEVSHIFT0X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLYV_VLOGIC 1V 0 1V_V1 V+ N774290 1;X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ :X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE/X_U9 CONTROL_HIZ N789513 1V 0 INVERTER3X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE L_L1 N778484 VOUT 1n &C_COUTH VOUT V+ 10p TC=0,0 &C_COUTL V- VOUT 10p TC=0,0 8X_SVOL N774212 N774290 V- N850209 Output_Stage_SVOL -R_ROUTL N850209 N778496 100 TC=0,0 .R_ROUTH N778496 N8555962 100 TC=0,0 9X_SVOH N774212 N774290 N8555962 V+ Output_Stage_SVOH .ENDS 9.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER 'V_VCMNP N20415 V-_BUFFER -300m&V_VCMPN N31340 V-_BUFFER 5.51@X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393&V_VCMPP N20155 V-_BUFFER 5.51'V_VCMNN N20539 V-_BUFFER -300mAX_U21 N31340 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393AX_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393AX_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393OX_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE .ENDS .SUBCKT Prop_Delay VIN VOUT ,T_TPD N03175 0 VOUT 0 Z0=50 TD=5u R_RT 0 VOUT 50 TC=0,0 $R_RS N03175 VIN 50 TC=0,0 .ENDS$.subckt Output_Stage_SMID 1 2 3 4 S_SMID 3 4 1 2 _SMIDRS_SMID 1 2 1G<.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SMID$.subckt Output_Stage_SHIZ 1 2 3 4 S_SHIZ 3 4 1 2 _SHIZRS_SHIZ 1 2 1G<.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SHIZ$.subckt Output_Stage_SVOL 1 2 3 4 S_SVOL 3 4 1 2 _SVOLRS_SVOL 1 2 1G<.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_SVOL$.subckt Output_Stage_SVOH 1 2 3 4 S_SVOH 3 4 1 2 _SVOHRS_SVOH 1 2 1G<.MODEL _SVOH VSWITCH Roff=1e12 Ron=1.0 Voff=0 Von=1.ends Output_Stage_SVOH1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS*$8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWS*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }:E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) } R1 3 2 1*C1 2 0 1e-12.ENDS*$.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS*$.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS*$.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$$.SUBCKT Difference 1 2 OUT VDD VSS "EOUT OUT1 0 VALUE = { V(1)- V(2)}R1 OUT1 OUT 1*C1 OUT 0 1e-12.ENDS*$,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)}.ENDS*$#.SUBCKT VCC_Range 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }R1 OUT OUT2 1C1 OUT 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS*$".SUBCKT 4ORGATE 1 2 3 4 5 VDD VSSE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 5 6 1.ENDS*$.subckt DESD AN CAT + params: + AREA=1.0 + IS=10f+ RS=5 + BV=100D_DESD AN CAT model22 {area} .model model22 d + is={IS} + rs={RS} + bv={BV} .ends DESD.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDSIN1IN2V+V-OUT1OUT2-Bv8 INT/RSTnT_100B1C0020240227115910 NOPCB (VF)BtH_INTnT_100B048020240227115910 NOPCB (VF)BnX 3V3T_0C4AFF1020240227115909 NOPCB (J)Bn 3V3T_0C4AF93020240227115909 NOPCB (J)Bpx( M_INTT_0C4AE79020240227115909 NOPCB (J)Bn 1V8T_0C4AE1B020240227115909 NOPCB (J)Bnp 3V3T_0C4E40C020240227115909 NOPCB (J)Bq(( H_RSTnT_0C4E3AE020240227115909 NOPCB (J)Bn 2V5T_0C4E350020240227115909 NOPCB (J)BnP 2V5T_0C4E2F2020240227115909 NOPCB (J)BnREFT_0C4E294020240227115909 NOPCB (J)Bq H_RSTnT_0C4E236020240227115909 NOPCB (J)Bp M_INTT_0C4E1D8020240227115909 NOPCB (J)Bn REFT_0C4E17A020240227115909 NOPCB (J)Bn 1V8T_0C4B4B7020240227120216 NOPCB (J)Bn @ 3V3T_0439D2B020240227120733 NOPCB (J)Bq( H_LPWnT_0439CCD020240227120733 NOPCB (J)BnX 3V3T_0439C11020240227120733 NOPCB (J)Bq H_LPWnT_0439B55020240227120733 NOPCB (J)BnX2V5T_043A369020240227120733 NOPCB (J)Bn REFT_0A64CF2020240227133926 NOPCB (J)BnREFT_098B03D020240227134135 NOPCB (J)Bn 3V3T_0C4E46A020240227115909 NOPCB (J)Bn 3V3T_1BF4E86020240227163154 NOPCB (J)BfXT_100AC9C020240227115707 NOPCB (GND)BfXT_0C4B459020240227115909 NOPCB (GND)BfxpT_0C4B33F020240227115909 NOPCB (GND)BfT_0C4B2E1020240227115909 NOPCB (GND)Bf8T_0C4B1C7020240227115909 NOPCB (GND)Bf(pT_0C4B10B020240227115909 NOPCB (GND)BfT_0C4B0AD020240227115909 NOPCB (GND)Bf T_04167B9020240227120732 NOPCB (GND)BfpT_041675B020240227120732 NOPCB (GND)BfT_041669F020240227120732 NOPCB (GND)BfT_0416641020240227120732 NOPCB (GND)Bf`T_04165E3020240227120732 NOPCB (GND)BfT_098AFDF020240227134131 NOPCB (GND)BfT_0C4B169020240227115909 NOPCB (GND)BfT_0C4B39D020240227115909 NOPCB (GND)BfxT_0AEB45D020240227140733 NOPCB (GND)8?  ]@"MbP??ư>'dd?Y@[dddd$@?.A.A.AeAMbP?@@?,C6:?ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname