OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.150.328 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$Mk??pppT_05D4C96020200317161954;HHHHT_05D4BE2020200317161954;ppT_05D4BA6020200317161954;00T_05D4B6A020200317161954;00T_05D4B2E020200317161954;T_05D4AF2020200317161954;p p(p p(T_05D4A7A020200317161954;PPPPT_05D4A02020200317161954;PPPPPPT_05D49C6020200317161954;T_05D4912020200317161954;H8H H8H T_07A7CE3020200317164022;H`HH`HT_09F3107020200317164025;T_0ABE11B020200319113032;T_0ABE0DF020200319113032;T_0ABE0A3020200319113032;T_0AB3B37020200319113039;T_08F648B020200319113518;hphpT_03F4902020200608095043;pxpxT_03F3D83020200608095045CPPhPPPPPhT_041363B020200608095515;p(p`p(p`T_046F4B8020200608123428BqVF3T_036CD21020200317065446 NOPCB (VF)BqVF1T_036CDDD020200317065446 NOPCB (VF) BR1T_036CE3B020200317065446R_AX600_W200 (R)@@@?Y@DBP V3T_036CF55020200317065446Battery_9V_V (V)ffffff @:B%PU1T_05CC06D020200317065409 TLV7041SC:\Users\a0226796\AppData\Local\Temp\DesignSoft\{Tina9-TI-11292018-112050}\TLV7021SCK#U##xxd*In+XCF01SVO204p  @d*In-` @d*Out  @d*V+0<  @d*V-h/C  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?ip@ip@ * source TLV7041$.SUBCKT TLV7041 IN+ IN- OUT V+ V- +X_U1 IN+ IN- OUT V+ V- TOPLEVELSCHEMATIC .ENDS ..SUBCKT TOPLEVELSCHEMATIC IN+ IN- OUT V+ V- IX_U7 IN+_BUFF IN-_BUFF N00308 V+_BUFF V-_BUFF N00366 HPA_COMPHYS;X_U4 IN-_BUFF IN+_BUFF N00323 V+_BUFF V-_BUFF INPUTRANGE X_U16 N19740 V+_BUFFER INP INPNEW N194834 0 INPNEWPORV_V3 N194834 0 5V_V1 N19288 0 1.6V5X_U14 N19288 N19122 N19740 N19358 0 PORCHECKHX_U13 V+_BUFFER V-_BUFFER N19122 V+_BUFFER V-_BUFFER DIFFERENCE>X_U15 N19740 V-_BUFFER INN INNNEW N194424 0 INNNEWPORV_V4 N194424 0 5.ENDS .SUBCKT PROPDELAY VIN VOUT (T_T1 VIN 0 VOUT 0 Z0=50 TD=3u R_R1 0 VOUT 50 TC=0,0 .ENDS 1.SUBCKT SUPPLYBUFFER V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS -.SUBCKT SUPPLYRANGE EN V+_BUFFER V-_BUFFER @X_U5 N18928 N18958 N18940 V+_BUFFER V-_BUFFER VCC_RANGEV_V4 N19230 0 -.3AX_U15 N18958 N19230 N19104 V+_BUFFER V-_BUFFER VCC_RangeV_V5 N19172 0 5V_V1 N18928 0 7HX_U13 V+_BUFFER V-_BUFFER N18958 V+_BUFFER V-_BUFFER DIFFERENCEDX_U17 N19100 0 N19172 EN V+_BUFFER V-_BUFFER ENABLE_TLV7021@X_U16 N18940 N19104 N19100 V+_BUFFER V-_BUFFER ANDGATE.ENDS +.SUBCKT INBUFF IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS >.SUBCKT OUTPUTSTAGE EN INRANGE V+_BUFFER V-_BUFFER VIN VOUT V_V3 5V 0 5KX_U3 VIN N772678 V+_BUFFER V-_BUFFER N772534 V-_BUFFER DIGLEVSHIFT-Q_Q1 N775848 N773140 V-_BUFFER NPN1 ,X_U8 INRANGE EN CONTROL 5V 0 ORGATE!V_V1 N772534 V+_BUFFER 18X_U5 N772678 N773140 N772534 V-_BUFFER INVERTER4X_U7 N776980 V+_BUFFER V-_BUFFER MID_SUPPLY.X_S3 CONTROL 0 N776699 MID OUTPUTSTAGE_S3 /X_S4 CONTROL 0 VOUT N775848 OUTPUTSTAGE_S4 V_V4 N776980 MID -0.7"D_D1 N776699 VOUT Dbreak .ENDS 9.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER >X_U18 N24659 N24743 N24733 V+_BUFFER V-_BUFFER ORGATE@X_U2 N24835 INN N24743 V+_BUFFER V-_BUFFER VINRANGE_393"V_V3 N25117 V-_BUFFER -.3>X_U19 N25095 N25203 N24963 V+_BUFFER V-_BUFFER ORGATE"V_V4 N25311 V-_BUFFER -.3@X_U1 N24639 INP N24659 V+_BUFFER V-_BUFFER VINRANGE_393V_V1 N24639 0 6LX_U20 N24733 N24963 0 N26592 INRANGE V+_BUFFER V-_BUFFER ORGATE1701@X_U3 INP N25117 N25095 V+_BUFFER V-_BUFFER VINRANGE_393V_V5 N26592 0 5V_V2 N24835 0 6AX_U17 INN N25311 N25203 V+_BUFFER V-_BUFFER VINRANGE_393.ENDS!.subckt OUTPUTSTAGE_S3 1 2 3 4 S_S3 3 4 1 2 _S3RS_S3 1 2 1G:.MODEL _S3 VSWITCH Roff=1e12 Ron=1.0 Voff=0 Von=5.ends OUTPUTSTAGE_S3!.subckt OUTPUTSTAGE_S4 1 2 3 4 S_S4 3 4 1 2 _S4RS_S4 1 2 1G:.MODEL _S4 VSWITCH Roff=1e12 Ron=1.0 Voff=5 Von=0.ends OUTPUTSTAGE_S4).SUBCKT ANDGATE3_LOGIC 1 2 3 OUT VDD VSSEOUT OUT 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 ) & (V(3)> (V(VDD)+V(VSS))/2)), V(VDD), V(VSS) ) }C1 OUT 0 1e-12.ENDS.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS.SUBCKT CMPOS 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(VSS), V(2) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS#.SUBCKT CMPOS_INN 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(VDD), V(2) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }^EINNNEW INNNEW 0 VALUE = { IF( ( V(OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWRE1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) } R1 3 2 1 C1 2 0 1e-12.ENDS&.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS$.SUBCKT IBias_AND 1 2 3 OUT VDD VSS=EOUT OUT 0 VALUE = { IF( (V(1) & V(2)) >= (V(3)), VSS, VDD)}C1 OUT 0 1e-12.ENDS#.SUBCKT IBias_OR 1 2 3 OUT VDD VSS=EOUT OUT 0 VALUE = { IF( (V(1) & V(2)) >= (V(3)), VDD, VSS)}C1 OUT 0 1e-12.ENDS.SUBCKT VIN_INV 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 2 0 1e-12.ENDS.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS(.SUBCKT SupplyEnable 1 2 3 OUT VDD VSS PEOUT OUT 0 VALUE = { IF( ((V(3) >= V(2) ) & (V(3) <= V(1))), V(VDD), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS$.SUBCKT Difference 1 2 OUT VDD VSS !EOUT OUT 0 VALUE = { V(1)- V(2)} R1 OUT 2 1 C1 2 0 1e-12.ENDS,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)} C1 2 0 1e-12.ENDS#.SUBCKT VCC_Range 1 2 OUT VDD VSS >EOUT OUT 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS >EOUT OUT 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS .SUBCKT HPA_INV 1 2 OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }lEOUT OUT 0 VALUE = { IF((V(1) < V(VMID)),V(2), IF( ((V(2) > V(VMID)) & (V(1) > V(VMID))), V(VSS), V(VDD)))} C1 2 0 1e-12.ENDS(.SUBCKT INPUTBUFFER 1 2 INPBUF INNBUF EINPBUF INPBUF 0 VALUE = {V(1)} EINNBUF INNBUF 0 VALUE = {V(2)} C1 2 0 1e-12.ENDS*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 } V(VMID) ), V(2), V(3) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS%.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }*d@Y@VG1[dddd$@?.A.A.AeAMbP?@@?@ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname