OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.150.328 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$Mk?;ppT_05D4C96020200317161954;HHHHT_05D4C1E020200317161954;HHHHT_05D4BE2020200317161954;ppT_05D4BA6020200317161954;00T_05D4B6A020200317161954;00T_05D4B2E020200317161954;T_05D4AF2020200317161954;p p`p p`T_05D4A7A020200317161954;T_05D4A3E020200317161954;PPT_05D498A020200317161954;H8H H8H T_07A7CE3020200317164022;H`HH`HT_09F3107020200317164025;T_0ABE11B020200319113032;T_0ABE0DF020200319113032;T_0ABE0A3020200319113032;T_0AB3B37020200319113039CPhPPPhT_08FCB99020200319113042;T_08F648B020200319113518BrH AM1T_036CCC3020200317065446 Amet (AM)BqVF3T_036CD21020200317065446 NOPCB (VF)BqVF1T_036CDDD020200317065446 NOPCB (VF)BpVG1T_036CE99020200317065446 Sgen (VG)@?j@VDB V2T_036CFB3020200317065446Battery_9V_V (V)@DBH8 V4T_09D48BA020200317164020Battery_9V_V (V) BhR2T_08EE20C020200319113032R_AX600_W200 (R)@@?Y@ BR3T_08EE26A020200319113032R_AX600_W200 (R)@@?Y@BqVF2T_08EE150020200319113516 NOPCB (VF):BPU1T_12AE33E020200402150907 TLV7031SC:\Users\a0226796\AppData\Local\Temp\DesignSoft\{Tina9-TI-11292018-112050}\TLV7021SCK#U##xxd*In+XCF01SVO204p  @d*In-` @d*Out  @d*V+0<  @d*V-h/C  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?'#tr@'#tr@* source TLV7031$.SUBCKT TLV7031 IN+ IN- OUT V+ V- -X_U1 IN+ IN- OUT V+ V- Top_Level_Schematic .ENDS 0.SUBCKT Top_Level_Schematic IN+ IN- OUT V+ V- 'X_U6 N33393 N33342 Propagation_Delay +X_U1 V+ V+_BUFF V- V-_BUFF Supply_Buffer V_V1 N332115 0 10mJX_U5 IN+_BUFF IN-_BUFF N33393 V+_BUFF V-_BUFF N332115 HPA_COMPHYS9X_U3 IN-_BUFF IN+_BUFF N33346 V+_BUFF V-_BUFF Vinrange =X_U7 N33335 N33346 V+_BUFF V-_BUFF N33342 OUT Output_Stage ,X_U2 N33335 V+_BUFF V-_BUFF Supply_Enable -X_U8 IN+ IN+_BUFF IN- IN-_BUFF InputBuffer I_I1 V+ 0 DC 315n .ENDS 0.SUBCKT InputBuffer IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS /.SUBCKT Supply_Enable EN V+_BUFFER V-_BUFFER @X_U5 N17617 N17647 N17629 V+_BUFFER V-_BUFFER VCC_RANGEV_V1 N17617 0 5.5HX_U13 V+_BUFFER V-_BUFFER N17647 V+_BUFFER V-_BUFFER DIFFERENCEAX_U15 N17647 N17841 N17795 V+_BUFFER V-_BUFFER VCC_Range@X_U16 N17629 N17795 N18229 V+_BUFFER V-_BUFFER ANDGATEV_V4 N17841 0 1.65DX_U17 N18229 0 N18343 EN V+_BUFFER V-_BUFFER ENABLE_TLV7021V_V5 N18343 0 1.ENDS ?.SUBCKT Output_Stage EN INRANGE V+_BUFFER V-_BUFFER VIN VOUT 8X_U5 N769278 N769284 N769130 V-_BUFFER INVERTER*Q_Q2 VOUT N769290 V+_BUFFER PNP1 R_R1 0 VOUT 1k TC=0,0 3X_S4 CONTROL 0 N769708 N769702 Output_Stage_S4 KX_U3 VIN N769278 V+_BUFFER V-_BUFFER N769130 V-_BUFFER DIGLEVSHIFT,X_S3 CONTROL 0 VOUT MID Output_Stage_S3 8X_U6 N769696 N769702 N769498 V-_BUFFER INVERTER!V_V1 N769130 V+_BUFFER 1!V_V2 N769498 V-_BUFFER 1*Q_Q1 VOUT N769708 V-_BUFFER NPN1 3X_S5 CONTROL 0 N769290 N769284 Output_Stage_S5 KX_U4 VIN N769696 V+_BUFFER V-_BUFFER N769498 V-_BUFFER DIGLEVSHIFT0X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLY,X_U8 INRANGE EN CONTROL 1V 0 ORGATEV_V3 1V 0 1.ENDS 7.SUBCKT Vinrange INN INP INRANGE V+_BUFFER V-_BUFFER @X_U2 N22942 INN N22852 V+_BUFFER V-_BUFFER VINRANGE_393"V_V4 N23434 V-_BUFFER -.3LX_U20 N22842 N23070 0 N23134 INRANGE V+_BUFFER V-_BUFFER ORGATE1701V_V1 N22748 0 6@X_U1 N22748 INP N22768 V+_BUFFER V-_BUFFER VINRANGE_393V_V5 N23134 0 1@X_U3 INP N23222 N23200 V+_BUFFER V-_BUFFER VINRANGE_393AX_U17 INN N23434 N23308 V+_BUFFER V-_BUFFER VINRANGE_393V_V2 N22942 0 6>X_U18 N22768 N22852 N22842 V+_BUFFER V-_BUFFER ORGATE"V_V3 N23222 V-_BUFFER -.3>X_U19 N23200 N23308 N23070 V+_BUFFER V-_BUFFER ORGATE.ENDS 2.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS %.SUBCKT Propagation_Delay VIN VOUT (T_T1 VIN 0 VOUT 0 Z0=50 TD=3u R_R1 0 VOUT 50 TC=0,0 .ENDS".subckt Output_Stage_S4 1 2 3 4 S_S4 3 4 1 2 _S4RS_S4 1 2 1G:.MODEL _S4 VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_S4".subckt Output_Stage_S3 1 2 3 4 S_S3 3 4 1 2 _S3RS_S3 1 2 1G:.MODEL _S3 VSWITCH Roff=1e12 Ron=1.0 Voff=0 Von=1.ends Output_Stage_S3".subckt Output_Stage_S5 1 2 3 4 S_S5 3 4 1 2 _S5RS_S5 1 2 1G:.MODEL _S5 VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0.ends Output_Stage_S5'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS.SUBCKT MID_SUPPLY OUT VDD VSS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }EOUT OUT 0 VALUE = {V(VMID)}.ENDS&.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }>EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS >EOUT OUT 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWRE1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) } R1 3 2 1 C1 2 0 1e-12.ENDS1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }^EINNNEW INNNEW 0 VALUE = { IF( ( V(OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 1e-12.ENDS.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS$.SUBCKT Difference 1 2 OUT VDD VSS !EOUT OUT 0 VALUE = { V(1)- V(2)} R1 OUT 2 1 C1 2 0 1e-12.ENDS,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)} C1 2 0 1e-12.ENDS*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 } V(VMID) ), V(2), V(3) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS#.SUBCKT VCC_Range 1 2 OUT VDD VSS >EOUT OUT 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS4.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n 4.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n In+In-OutV+V-BmHVsT_036D06F020200317065446 NOPCB (J)BmPVsT_036D0CD020200317065446 NOPCB (J)BnIN-T_08EE2C8020200319113032 NOPCB (J)BnIN-T_0912EDB020200319114548 NOPCB (J)Bfp`T_036D1E7020200317065446 NOPCB (GND)BfT_036D2A3020200317065446 NOPCB (GND)BfHT_09CBB6B020200317070008 NOPCB (GND)BfT_08EE1AE020200319113035 NOPCB (GND)8? ]@"MbP??ư>*d@Y@VG1[dddd$@?.A.A.AeAMbP?@@?,C6 ?ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname