OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.200.277 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$?VER=1.0Font0=Verdana,14Font1=Verdana,14,BRect0=2,0,0,85,22Rect1=1,0,0,85,10Rect2=1,0,10,10,17Rect3=1,10,10,75,17Rect4=1,75,10,85,17Rect5=1,0,17,50,22Rect6=1,50,17,85,22Text0=0,2,2,TitleText1=0,2,11,SizeText2=0,2,18,DateText3=0,12,11,Document No.Text4=0,77,11,RevText5=0,52,18,SheetText6=0,70,18,ofField0=1,T,11,2,80Field1=1,T,11,5,80Field2=1,S,4,13,5Field3=1,T,14,13,40Field4=1,R,78,13,6Field5=1,D,12,18,30Field6=1,P,64,18,3Field7=1,A,77,18,3#F0=LMV116 TINA-TI Reference DesignF3=Datasheet: n/a EVM: n/aF4=BF5=April 16, 2020F6=1F7=17F1=based on Green-Williams-Lis PSpice simulation model F@F Arial*LMV116 TINA-TI Reference Design based on *Green-William-Lis Pspice simulation modelSymbol????333333??M9r@9r Arial* LMV116 - Rev. A'* Created by Bala Ravi; April 16, 2020B* Created with Green-Williams-Lis Op Amp Macro-model Architecture2* Copyright 2018 by Texas Instruments Corporation7******************************************************$* MACRO-MODEL SIMULATED PARAMETERS:7******************************************************D* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)* UNITY GAIN BANDWIDTH (GBW)9* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)4* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)%* DIFFERENTIAL INPUT IMPEDANCE (Zid)$* COMMON-MODE INPUT IMPEDANCE (Zic)0* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)+* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)1* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)1* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)/* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)%* SHORT-CIRCUIT OUTPUT CURRENT (Isc)* QUIESCENT CURRENT (Iq))* SETTLING TIME VS. CAPACITIVE LOAD (ts)* SLEW RATE (SR)-* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD* LARGE SIGNAL RESPONSE* OVERLOAD RECOVERY TIME (tor)* INPUT BIAS CURRENT (Ib)* INPUT OFFSET CURRENT (Ios)* INPUT OFFSET VOLTAGE (Vos)(* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)C* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm))* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)Symbol????333333??;T_04F319C020200416025247;    T_04F3160020200416025247; h  h T_04F3124020200416025247?HhXpHhXhXpT_0506458020200416025247?HXHXXT_05063A4020200416025247;HHT_050650C020200416025247?T_0506548020200416025247;T_0506584020200416025247?00T_05065C0020200416025247;T_05065FC020200416025247?``T_0506638020200416025247;`X`XT_0506674020200416025247;    T_05066B0020200416025247;    T_05066EC020200416025247?(@ h(@ @ hT_0506728020200416025247?P@`HP@`@`HT_0506764020200416025247;T_05067A0020200416025247;88T_05067DC020200416025247;T_0506818020200416025247DB  VccT_079BBCC020180215122906 JP100 (V)@DBP@VeeT_079BB6E020180215122906 JP100 (V)@ B8RFT_079BB10020180215122906R_AX600_W200 (R)@@?fffffqY@B0 VinT_079BAB2020180215122906 JP100 (VG)?@@V BRIT_079BA54020180215122906R_AX600_W200 (R)@@@?fffffqY@BqVosT_079B9F6020180215122906 NOPCB (VF) B C2T_0F056F0020180215123248CP_CYL300_D700_L1400 (C) Iz>@eAY@? B hC3T_0F05692020180215123248CP_CYL300_D700_L1400 (C) Iz>@eAY@?BrVoutT_0F057AC020180215123307 NOPCB (VF):B|7(U1T_04EDDE5020200416025844 LMV116LMV116RC:\Users\a0227579\AppData\Local\Temp\DesignSoft\{Tina9-TI-09052019-154922}\LMV116SCK#LMV116Label#PP(d*IN+  @d*IN-pJ@; @d*OUT,  @d*VCCptJEz,  @d*VEE8  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?#t@#t@* LMV116 - Rev. A'* Created by Bala Ravi; April 16, 2020B* Created with Green-Williams-Lis Op Amp Macro-model Architecture2* Copyright 2020 by Texas Instruments Corporation7******************************************************$* MACRO-MODEL SIMULATED PARAMETERS:7******************************************************D* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)* UNITY GAIN BANDWIDTH (GBW)9* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)4* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)%* DIFFERENTIAL INPUT IMPEDANCE (Zid)$* COMMON-MODE INPUT IMPEDANCE (Zic)0* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)+* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)1* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)1* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)/* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)%* SHORT-CIRCUIT OUTPUT CURRENT (Isc)* QUIESCENT CURRENT (Iq))* SETTLING TIME VS. CAPACITIVE LOAD (ts)* SLEW RATE (SR)-* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD* LARGE SIGNAL RESPONSE* OVERLOAD RECOVERY TIME (tor)* INPUT BIAS CURRENT (Ib)* INPUT OFFSET CURRENT (Ios)* INPUT OFFSET VOLTAGE (Vos)(* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)C* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm))* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)7******************************************************#.subckt LMV116 IN+ IN- VCC VEE OUT7******************************************************* MODEL DEFINITIONS:9.model BB_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=0):.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)?.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3)9.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)&.model R_NOISELESS RES(T_ABS=-273.15)7******************************************************I_OS ESDn MID 397NI_B 23 MID 400NV_GRp 53 MID 40V_GRn 54 MID -40V_ISCp 47 MID 35V_ISCn 48 MID -32V_ORn 31 VCLP -80V11 52 30 0V_ORp 29 VCLP 80V12 51 28 0V4 42 OUT 0VCM_MIN 75 VEE_B -300MVCM_MAX 76 VCC_B -1I_Q VCC VEE 600UV_OS 83 23 822.2U"Rsrc MID 21 R_NOISELESS 1 %G_adjust 21 MID ESDp MID -148.7M&R48 21 22 R_NOISELESS 100MEG C14 22 21 79.58F 'R49 MID 22 R_NOISELESS 44.46K -SW11 ESDp ESDn ESDp ESDn S_VSWITCH_1-SW10 ESDn ESDp ESDn ESDp S_VSWITCH_2+S5 VEE ESDp VEE ESDp S_VSWITCH_3+S4 VEE ESDn VEE ESDn S_VSWITCH_4+S2 ESDn VCC ESDn VCC S_VSWITCH_5+S3 ESDp VCC ESDp VCC S_VSWITCH_6C28 24 MID 1P #R77 25 24 R_NOISELESS 100 C27 26 MID 1P #R76 27 26 R_NOISELESS 100 "R75 MID 28 R_NOISELESS 1 GVCCS8 28 MID 29 MID -1"R74 30 MID R_NOISELESS 1 GVCCS7 30 MID 31 MID -1"R73 32 MID R_NOISELESS 1 )XVCCS_LIM_ZO 33 MID MID 32 VCCS_LIM_ZO_0Xi_nn ESDn MID FEMT_0Xi_np MID 23 FEMT_0Xe_n ESDp 23 VNSE_0C25 34 MID 3.183F %R69 MID 34 R_NOISELESS 1MEG #GVCCS6 34 MID VSENSE MID -1UC20 CLAMP MID 125P (R68 MID CLAMP R_NOISELESS 1MEG *XVCCS_LIM_2 35 MID MID CLAMP VCCS_LIM_2_0%R44 MID 35 R_NOISELESS 1MEG &XVCCS_LIM_1 36 37 MID 35 VCCS_LIM_1_0$R72 33 MID R_NOISELESS 2.5 C26 33 38 63.66F #R71 33 38 R_NOISELESS 10K "R70 38 MID R_NOISELESS 1 GVCCS5 38 MID 39 MID -1C23 40 MID 31.83F #R67 39 40 R_NOISELESS 10K &R66 39 41 R_NOISELESS 323.3K "R65 41 MID R_NOISELESS 1 #Rdummy MID 42 R_NOISELESS 2K #Rx 42 32 R_NOISELESS 20K %G_Aol_Zo 41 MID CL_CLAMP 42 -390&R61 MID 43 R_NOISELESS 4.45K C16 43 44 795.8F &R58 44 43 R_NOISELESS 100MEG &GVCCS2 44 MID VEE_B MID -471.7M"R57 MID 44 R_NOISELESS 1 $R56 MID 45 R_NOISELESS 10K C15 45 46 397.9F &R55 46 45 R_NOISELESS 100MEG &GVCCS1 46 MID VCC_B MID -142.7M"R54 MID 46 R_NOISELESS 1 .XIQPos VIMON MID MID VCC VCCS_LIMIT_IQ_0.XIQNeg MID VIMON VEE MID VCCS_LIMIT_IQ_0C_DIFF ESDp ESDn 4P 1XCL_AMP 47 48 VIMON MID 49 50 CLAMP_AMP_LO_0+SOR_SWp CLAMP 51 CLAMP 51 S_VSWITCH_7+SOR_SWn 52 CLAMP 52 CLAMP S_VSWITCH_8.XGR_AMP 53 54 55 MID 56 57 CLAMP_AMP_HI_0#R39 53 MID R_NOISELESS 1T #R37 54 MID R_NOISELESS 1T &R42 VSENSE 55 R_NOISELESS 1M C19 55 MID 1F "R38 56 MID R_NOISELESS 1 "R36 MID 57 R_NOISELESS 1 "R40 56 58 R_NOISELESS 1M "R41 57 59 R_NOISELESS 1M C17 58 MID 1F C18 MID 59 1F *XGR_SRC 58 59 CLAMP MID VCCS_LIM_GR_0"R21 49 MID R_NOISELESS 1 "R20 MID 50 R_NOISELESS 1 "R29 49 60 R_NOISELESS 1M "R30 50 61 R_NOISELESS 1M C9 60 MID 1F C8 MID 61 1F ,XCL_SRC 60 61 CL_CLAMP MID VCCS_LIM_4_0#R22 47 MID R_NOISELESS 1T #R19 MID 48 R_NOISELESS 1T 0XCLAWp VIMON MID 62 VCC_B VCCS_LIM_CLAW+_00XCLAWn MID VIMON VEE_B 63 VCCS_LIM_CLAW-_0%R12 62 VCC_B R_NOISELESS 1K "R16 62 64 R_NOISELESS 1M %R13 VEE_B 63 R_NOISELESS 1K "R17 65 63 R_NOISELESS 1M C6 65 MID 1F C5 MID 64 1F $G2 VCC_CLP MID 64 MID -1M(R15 VCC_CLP MID R_NOISELESS 1K $G3 VEE_CLP MID 65 MID -1M(R14 MID VEE_CLP R_NOISELESS 1K V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}OGVO- COM VO- VALUE = {IF(V(VIN,COM)V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}OGVO- COM VO- VALUE = {IF(V(VIN,COM)10E-3 | V(OLP,COM)>10E-3),1,0)}.ENDS*6.SUBCKT VCCS_EXT_LIM_0 VIN+ VIN- IOUT- IOUT+ VP+ VP-.PARAM GAIN = 1IG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}.ENDS*IN+IN-VCCVEEOUTBf T_079B998020180215122906 NOPCB (GND)Bf`HT_079B93A020180215122906 NOPCB (GND)Bf`T_079B8DC020180215122906 NOPCB (GND)BfT_079BC88020180215122906 NOPCB (GND)BfXT_0F05634020180215123248 NOPCB (GND)BfXpT_0F0580A020180215123328 NOPCB (GND)8?c ]@"MbP??ư>'dd?Y@[dddd@@?.AcA.AeAMbP?@@?Mb`?ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname