SNAS480N May 2010 – August 2015 ADC12D1000 , ADC12D1600
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: Static Converter
- 6.6 Electrical Characteristics: Dynamic Converter
- 6.7 Electrical Characteristics: Analog Input/Output and Reference
- 6.8 Electrical Characteristics: I-Channel To Q-Channel
- 6.9 Electrical Characteristics: Converter and Sampling Clock
- 6.10 Electrical Characteristics: Autosync Feature
- 6.11 Electrical Characteristics: Digital Control and Output Pin
- 6.12 Electrical Characteristics: Power Supply
- 6.13 Electrical Characteristics: AC
- 6.14 Timing Requirements: Serial Port Interface
- 6.15 Timing Requirements: Calibration
- 6.16 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1
Control Modes
- 7.5.1.1
Non-Extended Control Mode
- 7.5.1.1.1 Dual Edge Sampling Pin (DES)
- 7.5.1.1.2 Non-Demultiplexed Mode Pin (NDM)
- 7.5.1.1.3 Dual Data Rate Phase Pin (DDRPH)
- 7.5.1.1.4 Calibration Pin (CAL)
- 7.5.1.1.5 Calibration Delay Pin (CALDLY)
- 7.5.1.1.6 Power-Down I-Channel Pin (PDI)
- 7.5.1.1.7 Power-Down Q-Channel Pin (PDQ)
- 7.5.1.1.8 Test Pattern Mode Pin (TPM)
- 7.5.1.1.9 Full-Scale Input Range Pin (FSR)
- 7.5.1.1.10 AC-DC-Coupled Mode Pin (VCMO)
- 7.5.1.1.11 LVDS Output Common-Mode Pin (VBG)
- 7.5.1.2 Extended Control Mode
- 7.5.1.1
Non-Extended Control Mode
- 7.5.1
Control Modes
- 7.6 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- NXA|292
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
1 Features
- Configurable to Either 2.0/3.2 GSPS Interleaved or 1.0/1.6 GSPS Dual ADC
- Pin-Compatible With ADC10D1x00 and ADC12D1x00
- Internally Terminated, Buffered, Differential Analog Inputs
- Interleaved Timing Automatic and Manual Skew Adjust
- Test Patterns at Output for System Debug
- Programmable 15-bit Gain and 12-bit Plus Sign Offset
- Programmable tAD Adjust Feature
- 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
- AutoSync Feature for Multi-Chip Systems
- Single 1.9-V ± 0.1-V Power Supply
2 Applications
- Wideband Communications
- Data Acquisition Systems
- RADAR and LIDAR
- Set-Top Boxes
- Consumer RF
- Software Defined Radios
SPACE
3 Description
The 12-bit, 2.0/3.2 GSPS ADC12D1x00 device is the latest advance in TI's Ultra High-Speed ADC family and builds upon the features, architecture, and functionality of the 10-bit GHz family of ADCs.
The ADC12D1x00 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and support programmable common-mode voltage.
The ADC12D1x00 is packaged in a leaded or lead-free 292-pin thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| ADC12D1000 | BGA (292) | 27.00 mm × 27.00 mm |
| ADC12D1600 |
- For all available packages, see the orderable addendum at the end of the data sheet.
Simplified Block Diagram
Wideband Performance
