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SNAS519H July 2011 – August 2015 ADC12D1000RF , ADC12D1600RF

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

NXA|292
- MPBGAB2

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Supply Voltage (V_A, V_TC, V_DR, V_E)		2.2	V
Supply Difference - max(V_A/TC/DR/E) - min(V_A/TC/DR/E)	0	100	mV
Voltage on Any Input Pin (except V_IN±)	–0.15	(V_A + 0.15)	V
V_IN± Voltage	–0.5	2.5	V
Ground Difference - max(GND_TC/DR/E) – min(GND_TC/DR/E)	0	100	mV
Input Current at Any Pin⁽³⁾		±50	mA
ADC12D1x00RF Package Power Dissipation at T_A ≤ 85°C⁽³⁾		3.45	W
Storage Temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = GND_TC = GND_DR = GND_E = 0 V, unless otherwise specified.

(3) When the input voltage at any pin exceeds the power supply limits, that is, less than GND or greater than V_A, the current at that pin should be limited to 50 mA. In addition, overvoltage at a pin must adhere to the maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case.

4.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge⁽¹⁾	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽²⁾	±2500	V
		Charged device model (CDM), per JEDEC specification JESD22-C101⁽³⁾	±1000
		Machine model (MM)	±250

(1) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω. Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Ambient Temperature, T_A	ADC12D1x00RF (Standard JEDEC thermal model)	–40	85	°C
Junction Temperature, T_J			140	°C
Supply Voltage (V_A, V_TC, V_E)		1.8	2	V
Driver Supply Voltage (V_DR)		1.8	V_A	V
V_IN± Voltage⁽³⁾	DC-coupled	–0.4	2.4	V
V_IN± Differential Voltage⁽⁴⁾	DC-coupled at 100% duty cycle		1	V
	DC-coupled at 20% duty cycle		2
	DC-coupled at 10% duty cycle		2.8
V_IN± Current⁽³⁾	AC-coupled	–50	50	mA
V_IN± Power	Maintaining common-mode voltage, AC-coupled		15.3	dBm
V_IN± Power	Not maintaining common-mode voltage, AC-coupled		17.1	dBm
Ground Difference – max(GND_TC/DR/E) -min(GND_TC/DR/E)			0	V
CLK± Voltage		0	V_A	V
Differential CLK Amplitude		0.4	2	V_P-P
V_CMI Common-Mode Input Voltage		V_CMO – 150	V_CMO +150	mV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the Absolute Maximum Ratings. Recommended Operating Conditions indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0 V, unless otherwise specified.

(3) Proper common-mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(4) This rating is intended for DC-coupled applications; the voltages and duty cycles listed may be safely applied to VIN+/- for the lifetime of the part.

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC12D1x00RF	UNIT
		NXA [BGA]
		40 PINS
R_θJA	Junction-to-ambient thermal resistance	16	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	2.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

4.5 Electrical Characteristics: Static Converter

Unless otherwise specified, the following apply after calibration for V_A = V_DR = V_TC = V_E = 1.9 V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; C_L = 10 pF; Differential, AC-coupled Sine Wave Sampling Clock, f_CLK = 1600/1000 MHz at 0.5 V_P-P with 50% duty cycle (as specified); V_BG = Floating; Non-Extended Control Mode; Rext = Rtrim = 3300 Ω ± 0.1%; Analog Signal Source Impedance = 100-Ω Differential; Non-Demux Non-DES Mode; Duty Cycle Stabilizer on. All other limits T_A = 25°C, unless otherwise noted.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
	Resolution with No Missing Codes	T_A = T_MIN to T_MAX	12		bits
INL	Integral Non-Linearity (Best fit)	1 MHz DC-coupled over-ranged sine wave, T_A = 25°C	±2.5	±7.25	LSB
DNL	Differential Non-Linearity	1 MHz DC-coupled over-ranged sine wave, T_A = T_MIN to T_MAX	±0.4	±0.96	LSB
V_OFF	Offset Error		5		LSB
V_OFF_ADJ	Input Offset Adjustment Range	Extended Control Mode	±45		mV
PFSE	Positive Full-Scale Error	See ⁽⁴⁾		±25	mV
NFSE	Negative Full-Scale Error	See ⁽⁴⁾		±25	mV
	Out-of-Range Output Code⁽⁵⁾	(V_IN+) − (V_IN−) > + Full Scale, T_A = T_MIN to T_MAX	4095
	Out-of-Range Output Code⁽⁵⁾	(V_IN+) − (V_IN−) < − Full Scale, T_A = T_MIN to T_MAX	0

(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
ADC12D1000RF ADC12D1600RF 30164404.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).

(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4-8. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.

(5) This parameter is specified by design and is not tested in production.

4.6 Electrical Characteristics: Dynamic Converter⁽²⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
	Bandwidth	DESIQ MODE
		–3 dB⁽⁶⁾			1.75		GHz
		–6 dB			2.7		GHz
		DESI, DESQ MODE
		–3 dB⁽⁶⁾			1.2		GHz
		–6 dB			2.3		GHz
		–9 dB			2.7		GHz
		–12 dB			3		GHz
		NON-DES MODE, DESCLKIQ MODE
		–3 dB⁽⁶⁾			2.7		GHz
		–6 dB			3.1		GHz
		–9 dB			3.5		GHz
		–12 dB			4		GHz
	Gain Flatness	NON-DES MODE
		D.C. to Fs/2			±0.3		dB
		D.C. to Fs	ADC12D1600RF		±0.8		dB
		D.C. to Fs	ADC12D1000RF		±0.4		dB
		D.C. to 3Fs/2	ADC12D1600RF		±1		dB
		D.C. to 3Fs/2	ADC12D1000RF		±0.8		dB
		D.C. to 2Fs	ADC12D1600RF		±3.6		dB
		D.C. to 2Fs	ADC12D1000RF		±0.9		dB
		DESI, DESQ MODE
		D.C. to Fs/2	ADC12D1600RF		±2.2		dB
		D.C. to Fs/2	ADC12D1000RF		±1		dB
		D.C. to Fs	ADC12D1600RF		±7.4		dB
		D.C. to Fs	ADC12D1000RF		±2.7		dB
		DESIQ MODE
		D.C. to Fs/2	ADC12D1600RF		±0.9		dB
		D.C. to Fs/2	ADC12D1000RF		±0.7		dB
		D.C. to Fs	ADC12D1600RF		±5.4		dB
		D.C. to Fs	ADC12D1000RF		±1.3		dB
		DESCLKIQ MODE
		D.C. to Fs/2	ADC12D1600RF		±0.7
		D.C. to Fs/2	ADC12D1000RF		±0.6
		D.C. to Fs	ADC12D1600RF		±4.2
		D.C. to Fs	ADC12D1000RF		±0.9
CER	Code Error Rate				10^–18		Error/ Sample
IMD₃	3rd order Intermodulation Distortion	DES MODE
		F_IN = 2670 MHz ± 2.5 MHz at –13 dBFS	ADC12D1600RF		–76.7		dBFS
			ADC12D1600RF		–63.7		dBc
			ADC12D1000RF		–73		dBFS
			ADC12D1000RF		–60		dBc
		F_IN = 2070 MHz ± 2.5 MHz at –13 dBFS	ADC12D1600RF		–78.6		dBFS
			ADC12D1600RF		–65.6		dBc
			ADC12D1000RF		–77		dBFS
			ADC12D1000RF		–64		dBc
		F_IN = 2670 MHz ± 2.5 MHz at –16 dBFS	ADC12D1600RF		–82.7		dBFS
			ADC12D1600RF		–66.7		dBc
			ADC12D1000RF		–85		dBFS
			ADC12D1000RF		–69		dBc
		F_IN = 2070 MHz ± 2.5 MHz at –16 dBFS	ADC12D1600RF		–80.1		dBFS
			ADC12D1600RF		–64.1		dBc
			ADC12D1000RF		–83		dBFS
			ADC12D1000RF		–67		dBc
	Noise Floor Density	50-Ω single-ended termination, DES Mode	ADC12D1600RF		–154.6		dBm/Hz
			ADC12D1600RF		–153.6		dBFS/Hz
			ADC12D1000RF		–154		dBm/Hz
			ADC12D1000RF		–153		dBFS/Hz
NON-DES MODE⁽³⁾⁽⁵⁾⁽⁷⁾
ENOB	Effective Number of Bits	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		9.4		bits
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		9.6		bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		9.3		bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		9.6		bits
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF	8.6⁽¹⁾	9.2		bits
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF	8.7⁽¹⁾	9.4		bits
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		9		bits
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		9.3		bits
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600RF		8.8		bits
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000RF		9		bits
SINAD	Signal-to-Noise Plus Distortion Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		58		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		59.7		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		57.5		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		59.7		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF	53.5⁽¹⁾	57.4		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF	54.1⁽¹⁾	58.6		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		55.9		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		57.6		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600RF		54.9		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000RF		55.9		dB
SNR	Signal-to-Noise Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		59		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		60.1		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		58.6		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		60		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF	54.6⁽¹⁾	58.2		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF	55.1⁽¹⁾	58.8		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		57		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		58.2		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600RF		55.4		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000RF		56.1		dB
THD	Total Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		–65		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		–69.7		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		–64		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		–71.9		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		–64.9	–60⁽¹⁾	dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		–72	–61⁽¹⁾	dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		–62.4	8	dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		–66.		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600RF		–64.1		dB
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000RF		–69		dB
2nd Harm	Second Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		–78.6		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		–79.3		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		–83		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		–91.6		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		–74		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		–86.3		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		–70.6		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		–73		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600RF		–71		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000RF		–73.7		dBc
3rd Harm	Third Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		–67.5		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		–71.9		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		–64.4		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		–75.4		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		–71		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		–74.8		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		–63.2		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		–68.9		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600RF		–75.7		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000RF		–73.5		dBc
SFDR	Spurious-Free Dynamic Range	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		67.9		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		71.4		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		64.5		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		75		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF	58⁽¹⁾	66.7		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF	61⁽¹⁾	71.9		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		63.8		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		68.4		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1600RF		67.3		dBc
		A_IN = 1448 MHz at –0.5 dBFS	ADC12D1000RF		66.5		dBc
DES MODE⁽³⁾⁽⁴⁾⁽⁷⁾
ENOB	Effective Number of Bits	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		9.3		bits
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		9.5		bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		9.3		bits
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		9.4		bits
		A_IN = 498 MHz at –0.5 dBFS			9.3		bits
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		8.9		bits
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		8.8		bits
		A_IN = 1448 MHz at –0.5 dBFS			8.7		bits
SINAD	Signal-to-Noise Plus Distortion Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		57.9		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		58.7		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		57.5		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		58.2		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		57.5		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		57.7		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		55.1		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		54.8		dB
		A_IN = 1448 MHz at –0.5 dBFS			54.1		dB
SNR	Signal-to-Noise Ratio	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		58.8		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		59.2
		A_IN = 248 MHz at –0.5 dBFS			58.5		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		58.1		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		58		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		55.9		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		55		dB
		A_IN = 1448 MHz at –0.5 dBFS			54.3		dB
THD	Total Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		–65.2		dB
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		–68.1		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		–64.2		dB
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		–68.4		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		–66.2		dB
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		–68.3		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		–62.9		dB
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		–66.4		dB
		A_IN = 1448 MHz at –0.5 dBFS			–67		dB
2nd Harm	Second Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		–81.5		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		–87.4		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		–84.2		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		–77.1		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		–69.7		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		–73.4		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		–70.5		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		–76.4		dBc
		A_IN = 1448 MHz at –0.5 dBFS			–73.6		dBc
3rd Harm	Third Harmonic Distortion	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		–66		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		–69.3		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		–63.8		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		–73.3		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		–69.7		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		–72.6		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		–63.5		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		–69.9		dBc
		A_IN = 1448 MHz at –0.5 dBFS			–67.1		dBc
SFDR	Spurious-Free Dynamic Range	A_IN = 125 MHz at –0.5 dBFS	ADC12D1600RF		66.9		dBc
		A_IN = 125 MHz at –0.5 dBFS	ADC12D1000RF		69		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1600RF		65		dBc
		A_IN = 248 MHz at –0.5 dBFS	ADC12D1000RF		67.1		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1600RF		70.4		dBc
		A_IN = 498 MHz at –0.5 dBFS	ADC12D1000RF		65		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1600RF		64.1		dBc
		A_IN = 998 MHz at –0.5 dBFS	ADC12D1000RF		61.7		dBc
		A_IN = 1448 MHz at –0.5 dBFS			61.3		dBc

(1) T_A = T_MIN to T_MAX

(2) This parameter is specified by design and/or characterization and is not tested in production.

(3) The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic performance vs. temperature in Typical Characteristics to see typical performance from cold to room temperature (–40°C to 25°C).

(4) These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature is used to reduce the interleaving timing spur amplitude, which occurs at fs/2-fin, and thereby increase the SFDR, SINAD and ENOB.

(5) The Fs/2 spur was removed from all the dynamic performance specifications.

(6) The –3 dB point is the traditional Full-Power Bandwidth (FPBW) specification. Although the insertion loss is approximately half at this frequency, the dynamic performance of the ADC does not necessarily begin to degrade to a level below which it may be effectively used in an application. The ADC may be used at input frequencies above the –3 dB FPBW point, for example for the ADC12D1000RF, into the 5th Nyquist zone. Depending on system requirements, it is only necessary to compensate for the insertion loss.

(7) Typical dynamic performance is only tested at Fin = 498 MHz; other input frequencies are specified by design and / or characterization and are not tested in production.

4.7 Electrical Characteristics: Analog Input/Output and Reference

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_{IN_FSR}	Analog Differential Input Full Scale Range	NON-EXTENDED CONTROL MODE
		FSR Pin Low	540⁽¹⁾	600	660⁽¹⁾	mV_P-P
		FSR Pin High	740⁽¹⁾	800	860⁽¹⁾	mV_P-P
		EXTENDED CONTROL MODE
		FM(14:0) = 0000h		600		mV_P-P
		FM(14:0) = 4000h (default)		800		mV_P-P
		FM(14:0) = 7FFFh		1000		mV_P-P
C_IN	Analog Input Capacitance, Non-DES Mode⁽³⁾⁽⁴⁾	Differential		0.02		pF
	Analog Input Capacitance, Non-DES Mode⁽³⁾⁽⁴⁾	Each input pin to ground		1.6		pF
	Analog Input Capacitance, DES Mode⁽³⁾⁽⁴⁾	Differential		0.08		pF
	Analog Input Capacitance, DES Mode⁽³⁾⁽⁴⁾	Each input pin to ground		2.2		pF
R_IN	Differential Input Resistance		91⁽¹⁾	100	109⁽¹⁾	Ω
COMMON-MODE OUTPUT
V_CMO	Common-Mode Output Voltage	I_CMO = ±100 µA	1.15⁽¹⁾	1.25	1.35⁽¹⁾	V
TC_V_CMO	Common-Mode Output Voltage Temperature Coefficient	I_CMO = ±100 µA⁽²⁾		38		ppm/°C
V_{CMO_LVL}	V_CMO input threshold to set DC-coupling Mode	See ⁽²⁾		0.63		V
C_L_V_CMO	Maximum V_CMO Load Capacitance	See ⁽³⁾		80⁽¹⁾		pF
BANDGAP REFERENCE
V_BG	Bandgap Reference Output Voltage	I_BG = ±100 µA	1.15⁽¹⁾	1.25	1.35⁽¹⁾	V
TC_V_BG	Bandgap Reference Voltage Temperature Coefficient	I_BG = ±100 µA⁽²⁾		32		ppm/°C
C_L_V_BG	Maximum Bandgap Reference load Capacitance	See ⁽³⁾		80⁽¹⁾		pF

(1) T_A = T_MIN to T_MAX

(2) This parameter is specified by design and/or characterization and is not tested in production.

(3) This parameter is specified by design and is not tested in production.

(4) The differential and pin-to-ground input capacitances are lumped capacitance values from design.

4.8 Electrical Characteristics: I-Channel to Q-Channel

PARAMETER		TEST CONDITIONS	TYP	UNIT
	Offset Match	See ⁽¹⁾	2	LSB
	Positive Full-Scale Match	Zero offset selected in Control Register	2	LSB
	Negative Full-Scale Match	Zero offset selected in Control Register	2	LSB
	Phase Matching (I, Q)	f_IN = 1.0 GHz⁽¹⁾	< 1	Degree
X-TALK	Crosstalk from I-channel (Aggressor) to Q-channel (Victim)	Aggressor = 867 MHz F.S., Victim = 100 MHz F.S.	–70	dB
X-TALK	Crosstalk from Q-channel (Aggressor) to I-channel (Victim)	Aggressor = 867 MHz F.S., Victim = 100 MHz F.S.	–70	dB

(1) This parameter is specified by design and/or characterization and is not tested in production.

4.9 Electrical Characteristics: Sampling Clock

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{IN_CLK}	Differential Sampling Clock Input Level⁽²⁾	Sine Wave Clock Differential Peak-to-Peak	0.4⁽¹⁾	0.6	2⁽¹⁾	V_P-P
V_{IN_CLK}	Differential Sampling Clock Input Level⁽²⁾	Square Wave Clock Differential Peak-to-Peak	0.4⁽¹⁾	0.6	2⁽¹⁾
C_{IN_CLK}	Sampling Clock Input Capacitance⁽³⁾	Differential		0.1		pF
C_{IN_CLK}	Sampling Clock Input Capacitance⁽³⁾	Each input to ground		1		pF
R_{IN_CLK}	Sampling Clock Differential Input Resistance	See ⁽²⁾		100		Ω

(1) T_A = T_MIN to T_MAX

(2) This parameter is specified by design and/or characterization and is not tested in production.

(3) This parameter is specified by design and is not tested in production.

4.10 Electrical Characteristics: AutoSync Feature

PARAMETER		TEST CONDITIONS	TYP	UNIT
V_{IN_RCLK}	Differential RCLK Input Level⁽¹⁾	Differential Peak-to-Peak	360	mV_P-P
C_{IN_RCLK}	RCLK Input Capacitance⁽¹⁾	Differential	0.12	pF
C_{IN_RCLK}	RCLK Input Capacitance⁽¹⁾	Each input to ground	1	pF
R_{IN_RCLK}	RCLK Differential Input Resistance	See ⁽¹⁾	100	Ω
I_{IH_RCLK}	Input Leakage Current; V_IN = V_A		22	µA
I_{IL_RCLK}	Input Leakage Current; V_IN = GND		33	µA
V_{O_RCOUT}	Differential RCOut Output Voltage		–360	mV_P-P

(1) This parameter is specified by design and/or characterization and is not tested in production.

4.11 Electrical Characteristics: Digital Control and Output Pin

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
V_IH	Logic High Input Voltage		0.7×V_A⁽¹⁾			V
V_IL	Logic Low Input Voltage				0.3×V_A⁽¹⁾	V
I_IH	Input Leakage Current; V_IN = V_A			0.02		μA
I_IL	Input Leakage Current; V_IN = GND	FSR, CalDly, CAL, NDM, TPM, DDRPh, DES		–0.02		μA
		SCS, SCLK, SDI		–17		μA
		PDI, PDQ, ECE		–38		μA
C_{IN_DIG}	Digital Control Pin Input Capacitance⁽³⁾	Measured from each control pin to GND		1.5		pF
DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ)
V_OD	LVDS Differential Output Voltage	V_BG = Floating, OVS = High	400⁽¹⁾	630	800⁽¹⁾	mV_P-P
		V_BG = Floating, OVS = Low	230⁽¹⁾	460	630⁽¹⁾	mV_P-P
		V_BG = V_A, OVS = High		670		mV_P-P
		V_BG = V_A, OVS = Low		500		mV_P-P
ΔV_{O DIFF}	Change in LVDS Output Swing Between Logic Levels			±1		mV
V_OS	Output Offset Voltage⁽²⁾	V_BG = Floating		0.8		V
V_OS	Output Offset Voltage⁽²⁾	V_BG = V_A		1.2		V
ΔV_OS	Output Offset Voltage Change Between Logic Levels	See ⁽²⁾		±1		mV
I_OS	Output Short-Circuit Current⁽²⁾	V_BG = Floating; D+ and D− connected to 0.8 V		±4		mA
Z_O	Differential Output Impedance	See ⁽²⁾		100		Ω
V_OH	Logic High-Output Level	CalRun, I_OH = −100 µA,⁽²⁾ SDO, I_OH = −400 µA⁽²⁾		1.65		V
V_OL	Logic Low-Output Level	CalRun, I_OL = 100 µA,⁽²⁾ SDO, I_OL = 400 µA⁽²⁾		0.15		V
V_{CMI_DRST}	DCLK_RST Common-Mode Input Voltage	See ⁽²⁾		1.25		V
V_{ID_DRST}	Differential DCLK_RST Input Voltage	See ⁽²⁾		V_{IN_CLK}		V_P-P
R_{IN_DRST}	Differential DCLK_RST Input Resistance	See ⁽²⁾		100		Ω

(1) T_A = T_MIN to T_MAX

(2) This parameter is specified by design and/or characterization and is not tested in production.

(3) This parameter is specified by design and is not tested in production.

4.12 Electrical Characteristics: Power Supply

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
I_A	Analog Supply Current	PDI = PDQ = Low	ADC12D1600RF	1225		mA
		PDI = PDQ = Low	ADC12D1000RF	1140		mA
		PDI = Low; PDQ = High	ADC12D1600RF	670		mA
		PDI = Low; PDQ = High	ADC12D1000RF	625		mA
		PDI = High; PDQ = Low	ADC12D1600RF	670		mA
		PDI = High; PDQ = Low	ADC12D1000RF	625		mA
		PDI = PDQ = High		2.7		mA
I_TC	Track-and-Hold and Clock Supply Current	PDI = PDQ = Low	ADC12D1600RF	490		mA
		PDI = PDQ = Low	ADC12D1000RF	410		mA
		PDI = Low; PDQ = High	ADC12D1600RF	290		mA
		PDI = Low; PDQ = High	ADC12D1000RF	250		mA
		PDI = High; PDQ = Low	ADC12D1600RF	290		mA
		PDI = High; PDQ = Low	ADC12D1000RF	250		mA
		PDI = PDQ = High		0.65		µA
I_DR	Output Driver Supply Current	PDI = PDQ = Low		270		mA
		PDI = Low; PDQ = High		140		mA
		PDI = High; PDQ = Low		140		mA
		PDI = PDQ = High		6		µA
I_E	Digital Encoder Supply Current	PDI = PDQ = Low	ADC12D1600RF	105		mA
		PDI = PDQ = Low	ADC12D1000RF	55		mA
		PDI = Low; PDQ = High	ADC12D1600RF	50		mA
		PDI = Low; PDQ = High	ADC12D1000RF	30		mA
		PDI = High; PDQ = Low	ADC12D1600RF	50		mA
		PDI = High; PDQ = Low	ADC12D1000RF	30		mA
		PDI = PDQ = High		34		µA
I_TOTAL	Total Supply Current	1:2 DEMUX MODE PDI = PDQ = Low	ADC12D1600RF	2090	2310⁽¹⁾	mA
		1:2 DEMUX MODE PDI = PDQ = Low	ADC12D1000RF	1875	2105⁽¹⁾	mA
		NON-DEMUX MODE PDI = PDQ = Low	ADC12D1600RF	2075		mA
		NON-DEMUX MODE PDI = PDQ = Low	ADC12D1000RF	1800		mA
P_C	Power Consumption	1:2 DEMUX MODE
		PDI = PDQ = Low	ADC12D1600RF	4	4.4⁽¹⁾	W
		PDI = PDQ = Low	ADC12D1000RF	3.6	4⁽¹⁾	W
		PDI = Low; PDQ = High	ADC12D1600RF	2.2		W
		PDI = Low; PDQ = High	ADC12D1000RF	2		W
		PDI = High; PDQ = Low	ADC12D1600RF	2.2		W
		PDI = High; PDQ = Low	ADC12D1000RF	2		W
		PDI = PDQ = High		6.4		mW
		NON-DEMUX MODE
		PDI = PDQ = Low	ADC12D1600RF	3.94		W
		PDI = PDQ = Low	ADC12D1000RF	3.42		W

(1) T_A = T_MIN to T_MAX

4.13 Electrical Characteristics: AC

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SAMPLING CLOCK (CLK)
f_{CLK (max)}	Maximum Sampling Clock Frequency		ADC12D1600RF		1.6⁽¹⁾		GHz
f_{CLK (max)}	Maximum Sampling Clock Frequency		ADC12D1000RF		1⁽¹⁾		GHz
f_{CLK (min)}	Minimum Sampling Clock Frequency	Non-DES Mode; LFS = 0b			300⁽¹⁾		MHz
		Non-DES Mode; LFS = 1b			150⁽¹⁾		MHz
		DES Mode			500⁽¹⁾		MHz
	Sampling Clock Duty Cycle	f_CLK(min) ≤ f_CLK ≤ f_CLK(max)⁽³⁾		20%⁽¹⁾	50%	80%⁽¹⁾
t_CL	Sampling Clock Low Time	See ⁽²⁾	ADC12D1600RF	200⁽¹⁾	500		ps
t_CL	Sampling Clock Low Time	See ⁽²⁾	ADC12D1000RF	125⁽¹⁾	312.5		ps
t_CH	Sampling Clock High Time	See ⁽²⁾	ADC12D1600RF	200⁽¹⁾	500		ps
t_CH	Sampling Clock High Time	See ⁽²⁾	ADC12D1000RF	125⁽¹⁾	312.5		ps
DATA CLOCK (DCLKI, DCLKQ)
	DCLK Duty Cycle	See ⁽²⁾		45%⁽¹⁾	50%	55%⁽¹⁾
t_SR	Setup Time DCLK_RST±	See ⁽³⁾			45		ps
t_HR	Hold Time DCLK_RST±	See ⁽³⁾			45		ps
t_PWR	Pulse Width DCLK_RST±	See ⁽²⁾		5⁽¹⁾			Sampling Clock Cycles
t_{SYNC_DLY}	DCLK Synchronization Delay	90° Mode⁽²⁾		4⁽¹⁾			Sampling Clock Cycles
t_{SYNC_DLY}	DCLK Synchronization Delay	0° Mode⁽²⁾		5⁽¹⁾			Sampling Clock Cycles
t_LHT	Differential Low-to-High Transition Time	10%-to-90%, C_L = 2.5 pF⁽³⁾			200		ps
t_HLT	Differential High-to-Low Transition Time	10%-to-90%, C_L = 2.5 pF⁽³⁾			200		ps
t_SU	Data-to-DCLK Setup Time	DDR 90° Mode⁽²⁾	ADC12D1600RF		500		ps
t_SU	Data-to-DCLK Setup Time	DDR 90° Mode⁽²⁾	ADC12D1000RF		870		ps
t_H	DCLK-to-Data Hold Time	DDR 90° Mode⁽²⁾	ADC12D1600RF		500		ps
t_H	DCLK-to-Data Hold Time	DDR 90° Mode⁽²⁾	ADC12D1000RF		870		ps
t_OSK	DCLK-to-Data Output Skew	50% of DCLK transition to 50% of Data transition DDR 0° Mode, SDR Mode ⁽²⁾			±50		ps
DATA INPUT-TO-OUTPUT
t_AD	Aperture Delay⁽³⁾	Sampling CLK+ Rise to Acquisition of Data			1.29		ns
t_AJ	Aperture Jitter	See ⁽³⁾			0.2		ps (rms)
t_OD	Sampling Clock-to Data Output Delay (in addition to Latency)	50% of Sampling Clock transition to 50% of Data transition⁽³⁾			3.2		ns
t_LAT	Latency in 1:2 Demux Non-DES Mode⁽²⁾	DI, DQ Outputs		34⁽¹⁾			Sampling Clock Cycles
	Latency in 1:2 Demux Non-DES Mode⁽²⁾	DId, DQd Outputs		35⁽¹⁾
	Latency in 1:4 Demux DES Mode⁽²⁾	DI Outputs		34⁽¹⁾
		DQ Outputs		34.5⁽¹⁾
		DId Outputs		35⁽¹⁾
		DQd Outputs		35.5⁽¹⁾
	Latency in Non-Demux Non-DES Mode⁽²⁾	DI Outputs		34⁽¹⁾
	Latency in Non-Demux Non-DES Mode⁽²⁾	DQ Outputs		34⁽¹⁾
	Latency in Non-Demux DES Mode⁽²⁾	DI Outputs		34⁽¹⁾
	Latency in Non-Demux DES Mode⁽²⁾	DQ Outputs		34.5⁽¹⁾
t_ORR	Over Range Recovery Time ⁽³⁾	Differential V_IN step from ±1.2 V to 0 V to accurate conversion		1			Sampling Clock Cycles
t_WU	Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion)	Non-DES Mode⁽²⁾			500		ns
t_WU	Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion)	DES Mode⁽²⁾			1		µs

(1) T_A = T_MIN to T_MAX

(2) This parameter is specified by design and is not tested in production.

(3) This parameter is specified by design and/or characterization and is not tested in production.

4.14 Timing Requirements: Serial Port Interface

PARAMETER		TEST CONDITIONS	MIN	NOM	UNIT
f_SCLK	Serial Clock Frequency	See ⁽²⁾		15	MHz
	Serial Clock Low Time		30⁽¹⁾		ns
	Serial Clock High Time		30⁽¹⁾		ns
t_SSU	Serial Data-to-Serial Clock Rising Setup Time	See ⁽²⁾	2.5		ns
t_SH	Serial Data-to-Serial Clock Rising Hold Time	See ⁽²⁾	1		ns
t_SCS	SCS-to-Serial Clock Rising Setup Time	See ⁽³⁾		2.5	ns
t_HCS	SCS-to-Serial Clock Falling Hold Time	See ⁽³⁾		1.5	ns
t_BSU	Bus turnaround time	See ⁽³⁾		10	ns

(1) T_A = T_MIN to T_MAX

(2) This parameter is specified by design and is not tested in production.

(3) This parameter is specified by design and/or characterization and is not tested in production.

4.15 Timing Requirements: Calibration

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
t_CAL	Calibration Cycle Time	Non-ECM		4.1×10⁷		Sampling Clock Cycles
		ECM CSS = 0b
		ECM CSS = 1b
t_{CAL_L}	CAL Pin Low Time	See ⁽²⁾	1280⁽¹⁾			Sampling Clock Cycles
t_{CAL_H}	CAL Pin High Time	See ⁽²⁾	1280⁽¹⁾			Sampling Clock Cycles
t_CalDly	Calibration delay determined by CalDly Pin⁽²⁾	CalDly = Low			2²⁴⁽¹⁾	Sampling Clock Cycles
t_CalDly	Calibration delay determined by CalDly Pin⁽²⁾	CalDly = High			2³⁰⁽¹⁾	Sampling Clock Cycles

(1) T_A = T_MIN to T_MAX

(2) This parameter is specified by design and is not tested in production.

The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 4-1 Clocking in 1:2 Demux Non-DES Mode

Figure 4-2 Clocking in Non-Demux Non-DES Mode

Figure 4-3 Clocking in 1:4 Demux DES Mode

Figure 4-4 Clocking in Non-Demux Mode DES Mode

Figure 4-5 Data Clock Reset Timing (Demux Mode)

Figure 4-6 Power-on and On-Command Calibration Timing

Figure 4-7 Serial Interface Timing

Figure 4-8 Input / Output Transfer Characteristic

4.16 Typical Characteristics

V_A= V_DR = V_TC = V_E = 1.9 V, f_CLK = 1600 MHz / 1000 MHz for the ADC12D1600RF / ADC12D1000RF, respectively, f_IN = 498 MHz, T_A= 25°C, I-channel, Demux Non-DES Mode, unless otherwise stated.