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ZHCSAD3B January 2012 – December 2014

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- MPQF124G

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- QFND136Y

訂購(gòu)信息

8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Voltage range (with respect to GND)	VBUS	–2	22	V
	PMID	–0.3	22	V
	STAT, PG	–0.3	20	V
	BTST	–0.3	26	V
	SW	–2	20	V
	BAT, SYS (converter not switching)	–0.3	6	V
	SDA, SCL, INT, OTG, ILIM, REGN, TS1, TS2, CE, PSEL, D+, D–	–0.3	7	V
	BTST TO SW	–0.3	–7	V
	PGND to GND	–0.3	–0.3	V
Output sink current	INT, STAT, PG		6	mA
Junction temperature		–40°C	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_IN	Input voltage	3.9	17⁽¹⁾	V
I_IN	Input current		3	A
I_SYS	Output current (SYS)		4.5	A
V_BAT	Battery voltage		4.4	V
I_BAT	Fast charging current		4.5	A
I_BAT	Discharging current with internal MOSFET		6 (continuous) 9 (peak) (up to 1 sec duration)	A
T_A	Operating free-air temperature range	–40	85	°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq2419x	UNIT
THERMAL METRIC⁽¹⁾		RGE (24 PIN)	UNIT
R_θJA	Junction-to-ambient thermal resistance	32.2	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	29.8
R_θJB	Junction-to-board thermal resistance	9.1
ψ_JT	Junction-to-top characterization parameter	0.3
ψ_JB	Junction-to-board characterization parameter	9.1
R_θJCbot	Junction-to-case (bottom) thermal resistance	2.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V_{VBUS_UVLOZ} < V_VBUS < V_ACOV and V_VBUS > V_BAT + V_SLEEP, T_J = –40°C to 125°C and T_J = 25°C for typical values unless other noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
QUIESCENT CURRENTS
I_BAT	Battery discharge current (BAT, SW, SYS)	V_VBUS < V_UVLO, VBAT = 4.2 V, leakage between BAT and VBUS			5	µA
		High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1), –40°C to 85°C		12	20	µA
		High-Z Mode, or no VBUS, REG07[5] = 0, –40°C to 85°C		32	55	µA
I_VBUS	Input supply current (VBUS)	V_VBUS = 5 V, High-Z mode		15	30	µA
		V_VBUS = 17 V, High-Z mode		30	50	µA
		V_VBUS > V_UVLO, V_VBUS > V_BAT, converter not switching		1.5	3	mA
		V_VBUS > V_UVLO, V_VBUS > V_BAT, converter switching, V_BAT = 3.2 V, I_SYS = 0 A		4		mA
		V_VBUS > V_UVLO, V_VBUS > V_BAT, converter switching, V_BAT = 3.8 V, I_SYS = 0 A		15		mA
I_OTGBOOST	Battery discharge current in boost mode	VBAT = 4.2 V, Boost mode, I_VBUS = 0 A, converter switching		4		mA
VBUS/BAT POWER UP
V_{VBUS_OP}	VBUS operating range		3.9		17	V
V_{VBUS_UVLOZ}	VBUS for active I²C, no battery	V_VBUS rising	3.6			V
V_SLEEP	Sleep mode falling threshold	V_VBUS falling, V_VBUS-VBAT	35	80	120	mV
V_SLEEPZ	Sleep mode rising threshold	V_VBUS rising, V_VBUS-VBAT	170	250	350	mV
V_ACOV	VBUS over-voltage rising threshold	V_VBUS rising	17.4	18		V
V_{ACOV_HYST}	VBUS over-voltage falling hysteresis	V_VBUS falling		700		mV
V_{BAT_UVLOZ}	Battery for active I²C, no VBUS	V_BAT rising	2.3			V
V_{BAT_DPL}	Battery depletion threshold	V_BAT falling		2.4	2.6	V
V_{BAT_DPL_HY}	Battery depletion rising hysteresis	V_BAT rising		170	260	mV
V_VBUSMIN	Bad adapter detection threshold	V_VBUS falling		3.8		V
I_BADSRC	Bad adapter detection current source			30		mA
t_BADSRC	Bad source detection duration			30		ms
POWER PATH MANAGEMENT
V_{SYS_RANGE}	Typical system regulation voltage	Isys = 0 A, Q4 off, V_BATup to 4.2 V, REG01[3:1] = 101, V_SYSMIN = 3.5 V	3.5		4.35	V
V_{SYS_MIN}	System voltage output	REG01[3:1] = 101, V_SYSMIN = 3.5 V	3.55	3.65		V
R_ON(RBFET)	Internal top reverse blocking MOSFET on-resistance	Measured between VBUS and PMID		23	38	mΩ
R_ON(HSFET)	Internal top switching MOSFET on-resistance between PMID and SW	T_J = –40°C to 85°C		27	35	mΩ
R_ON(HSFET)		T_J = -40°C to 125°C		27	45	mΩ
R_ON(LSFET)	Internal bottom switching MOSFET on-resistance between SW and PGND	T_J = –40°C to 85°C		32	45	mΩ
R_ON(LSFET)		T_J = -40°C to 125°C		32	48	mΩ
V_FWD	BATFET forward voltage in supplement mode	BAT discharge current 10 mA		30		mV
V_{SYS_BAT}	SYS/BAT Comparator	V_SYS falling		90		mV
V_BATGD	Battery good comparator rising threshold	V_BAT rising		3.55		V
V_{BATGD_HYST}	Battery good comparator falling threshold	V_BAT falling		100		mV
BATTERY CHARGER
V_{BAT_REG_ACC}	Charge voltage regulation accuracy	V_BAT = 4.112 V and 4.208 V	–0.5%		0.5%
I_{ICHG_REG_ACC}	Fast charge current regulation accuracy	V_BAT = 3.8 V, I_CHG = 1792 mA, T_J = 25°C	–4%		4%
I_{ICHG_REG_ACC}	Fast charge current regulation accuracy	V_BAT = 3.8 V, I_CHG = 1792 mA, T_J = –20°C to 125°C	–7%		7%
I_{CHG_20pct}	Charge current with 20% option on	V_BAT = 3.1 V, I_CHG = 104 mA, REG02 = 03	75	100	150	mA
V_BATLOWV	Battery LOWV falling threshold	Fast charge to precharge, REG04[1] = 1	2.6	2.8	2.9	V
V_{BATLOWV_HYST}	Battery LOWV rising threshold	Precharge to fast charge, REG04[1] = 1	2.8	3.0	3.1	V
I_{PRECHG_ACC}	Precharge current regulation accuracy	VBAT = 2.6 V, I_CHG = 256 mA	–20%		20%
I_{TERM_ACC}	Termination current accuracy	I_TERM = 256 mA, I_CHG = 960 mA	–20%		20%
V_SHORT	Battery Short Voltage	VBAT falling		2.0		V
V_{SHORT_HYST}	Battery Short Voltage hysteresis	VBAT rising		200		mV
I_SHORT	Battery short current	VBAT < 2.2V		100		mA
V_RECHG	Recharge threshold below VBAT_REG	VBAT falling, REG04[0] = 0		100		mV
t_RECHG	Recharge deglitch time	VBAT falling, REG04[0] = 0		20		ms
R_{ON_BATFET}	SYS-BAT MOSFET on-resistance	T_J = 25°C		12	15	mΩ
R_{ON_BATFET}	SYS-BAT MOSFET on-resistance	T_J = –40°C to 125°C		12	20	mΩ
INPUT VOLTAGE/CURRENT REGULATION
V_{INDPM_REG_ACC}	Input voltage regulation accuracy	REG00[6:3] = 0110 (4.36 V) or 1011 (4.76 V)	–2%		2%
I_{USB_DPM}	USB Input current regulation limit, VBUS = 5 V, current pulled from SW	USB100	85		100	mA
		USB150	125		150	mA
		USB500	440		500	mA
		USB900	750		900	mA
I_{ADPT_DPM}	Input current regulation accuracy	Typical input current of 1.5 A based on KLIM	1.35	1.5	1.65	A
I_{IN_START}	Input current limit during system start up	VSYS < 2.2 V		100		mA
K_ILIM	I_IN = K_ILIM/R_ILIM	IINDPM = 1.5 A	435	485	530	A x Ω
D+/D- DETECTION
V_{D+_SRC}	D+ voltage source		0.5	0.6	0.7	V
I_{D+_SRC}	D+ connection check current source		7		14	µA
I_{D–_SINK}	D– current sink		50	100	150	µA
I_{D_LKG}	Leakage current into D+/D–	D–, switch open	–1		1	µA
I_{D_LKG}	Leakage current into D+/D–	D+, switch open	–1		1	µA
V_{D+_LOW}	D+ Low comparator threshold		0.7		0.8	V
V_{D–_LOWdatref}	D– Low comparator threshold		250		400	mV
R_{D–_DWN}	D– Pulldown for connection check		14.25		24.8	kΩ
t_{SDP_DEFAULT}	Charging timer with 100-mA USB host in default mode				45	mins
BAT OVER-VOLTAGE PROTECTION
V_BATOVP	Battery over-voltage threshold	V_BAT rising, as percentage of V_{BAT_REG}		104%
V_{BATOVP_HYST}	Battery over-voltage hysteresis	V_BAT falling, as percentage of V_{BAT_REG}		2%
t_BATOVP	Battery over-voltage deglitch time to disable charge			1		µs
THERMAL REGULATION AND THERMAL SHUTDOWN
T_{Junction_REG}	Junction temperature regulation accuracy	REG06[1:0] = 11		120		°C
T_SHUT	Thermal shutdown rising temperature	Temperature increasing		160		°C
T_{SHUT_HYS}	Thermal shutdown hysteresis			30		°C
	Thermal shutdown rising deglitch	Temperature increasing delay		1		ms
	Thermal shutdown falling deglitch	Temperature decreasing delay		1		ms
COLD/HOT THERMISTER COMPARATOR (bq24190,bq24192,bq24192I)
V_LTF	Cold temperature threshold, TS pin voltage rising threshold	Charger suspends charge. As percentage to V_REGN	73%	73.5%	74%
V_{LTF_HYS}	Cold temperature hysteresis, TS pin voltage falling	As percentage to V_REGN	0.2%	0.4%	0.6%
V_HTF	Hot temperature TS pin voltage rising threshold	As percentage to V_REGN	46.6%	47.2%	48.8%
V_TCO	Cut-off temperature TS pin voltage falling threshold	As percentage to V_REGN	44.2%	44.7%	45.2%
	Deglitch time for temperature out of range detection	V_TS > V_LTF, or V_TS < V_TCO, or V_TS < V_HTF		10		ms
CHARGE OVER-CURRENT COMPARATOR
I_{HSFET_OCP}	HSFET over-current threshold		5.3	7		A
I_{BATFET_OCP}	System over load threshold		9			A
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
V_{LSFET_UCP}	LSFET charge under-current falling threshold	From sync mode to non-sync mode		100		mA
PWM OPERATION
F_SW	PWM Switching frequency, and digital clock		1300	1500	1700	kHz
D_MAX	Maximum PWM duty cycle			97%
V_{BTST_REFRESH}	Bootstrap refresh comparator threshold	VBTST-VSW when LSFET refresh pulse is requested, VBUS = 5 V		3.6		V
V_{BTST_REFRESH}	Bootstrap refresh comparator threshold	VBTST-VSW when LSFET refresh pulse is requested, VBUS > 6 V		4.5		V
BOOST MODE OPERATION
V_{OTG_REG}	OTG output voltage	I(VBUS) = 0		5.00		V
V_{OTG_REG_ACC}	OTG output voltage accuracy	I(VBUS) = 0	–2%		2%
I_OTG	OTG mode output current	REG01[0] = 0	0.5			A
I_OTG	OTG mode output current	REG01[0] = 1	1.3			A
V_{OTG_OVP}	OTG over-voltage threshold			5.3	5.5	V
I_{OTG_ILIM}	LSFET cycle-by-cycle current limit		3.2	4.6		A
I_{OTG_HSZCP}	HSFET under current falling threshold			100		mA
I_{RBFET_OCP}	RBFET over-current threshold	REG01[0] = 1	1.4	1.8	2.7	A
I_{RBFET_OCP}	RBFET over-current threshold	REG01[0] = 0	0.6	1.1	1.8	A
REGN LDO
V_REGN	REGN LDO output voltage	V_VBUS = 10 V, I_REGN = 40 mA	5.6	6	6.4	V
V_REGN	REGN LDO output voltage	V_VBUS = 5 V, I_REGN = 20 mA	4.75	4.8		V
I_REGN	REGN LDO current limit	V_VBUS = 10 V, V_REGN = 3.8 V	50			mA
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, PSEL, STAT, PG)
V_ILO	Input low threshold				0.4	V
V_IH	Input high threshold		1.3			V
V_{OUT_LO}	Output low saturation voltage	Sink current = 5 mA			0.4	V
I_BIAS	High level leakage current	Pull up rail 1.8 V			1	µA
I²C INTERFACE (SDA, SCL, INT)
V_IH	Input high threshold level	VPULL-UP = 1.8 V, SDA and SCL	1.3			V
V_IL	Input low threshold level	VPULL-UP = 1.8 V, SDA and SCL			0.4	V
V_OL	Output low threshold level	Sink current = 5 mA			0.4	V
I_BIAS	High-level leakage current	VPULL-UP = 1.8 V, SDA and SCL			1	µA
f_SCL	SCL clock frequency				400	kHz
DIGITAL CLOCK AND WATCHDOG TIMER
f_HIZ	Digital crude clock	REGN LDO disabled	15	35	50	kHz
f_DIG	Digital clock	REGN LDO enabled	1300	1500	1700	kHz
t_WDT	REG05[5:4] = 11	REGN LDO enabled	136	160		sec

8.6 Typical Characteristics

Table 1. Table of Figures

	FIGURE NO.
System Light Load Efficiency vs System Load Current	Figure 1
SYS Voltage Regulation vs System Load	Figure 2
Charging Efficiency vs Charging Current	Figure 3
Boost Mode Efficiency vs VBUS Load Current	Figure 4
Boost Mode VBUS Voltage Regulation vs VBUS Load Current	Figure 5
SYS Voltage vs Temperature	Figure 6
BAT Voltage vs Temperature	Figure 7
Input Current Limit vs Temperature	Figure 8
Charge Current vs Temperature	Figure 9