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ZHCSG50B March 2016 – March 2017

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

YFF|42
- MXBG341

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	VALUE
Voltage range (with respect to GND)	VBUS (converter not switching)	–2	22	V
	PMID (converter not switching)	–0.3	22	V
	STAT	–0.3	20	V
	PG (bq25898)	–0.3	7	V
	PSEL (bq25898)	–0.3	7	V
	VOK (bq25898)	–0.3	7	V
	DSEL (bq25898D)	–0.3	7	V
	D+, D– (bq25898D)	–0.3	7	V
	BTST	–0.3	20	V
	SW	–3	16	V
	BAT, SYS (converter not switching)	–0.3	6	V
	SDA, SCL, INT, OTG, REGN, TS, CE, QON	–0.3	7	V
	BTST TO SW	–0.3	7	V
	PGND to GND	–0.3	0.3	V
	BATSEN	–0.3	7	V
	ILIM	–0.3	5	V
Output sink current	INT, STAT		6	mA
	PG (bq25898)		6	mA
	DSEL (bq25898D)		5	mA
	VOK (bq25898)		5	mA
Junction temperature		–40	150	°C
Storage temperature range, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

8.2 ESD Ratings

			VALUE	UNIT
V_ESD	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾	±2000	V
V_ESD	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_IN	Input voltage	3.9	14⁽¹⁾	V
I_IN	Input current (VBUS)		3.25	A
I_SYS	Output current (SW)		4	A
V_BAT	Battery voltage		4.608	V
I_BAT	Fast charging current		4	A
	Discharging current with internal MOSFET		Up to 6 (continuos)	A
	Discharging current with internal MOSFET		9 (peak) (Up to 1 sec duration)	A
T_A	Operating free-air temperature range	–40	85	°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq25898, bq25898D	UNIT
		YFF (DSBGA)
		42-BALL
R_θJA	Junction-to-ambient thermal resistance	53.5	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	0.2	°C/W
R_θJB	Junction-to-board thermal resistance	8.2	°C/W
ψ_JT	Junction-to-top characterization parameter	0.9	°C/W
ψ_JB	Junction-to-board characterization parameter	8.2	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

8.5 Electrical Characteristics

V_{VBUS_UVLOZ} < V_VBUS < V_ACOV and V_VBUS > V_BAT + V_SLEEP, T_J = –40°C to 125°C and T_J = 25°C for typical values (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
QUIESCENT CURRENTS
I_BAT	Battery discharge current (BAT, SW, SYS) in buck mode	V_BAT = 4.2 V, V_(VBUS) < V_(UVLO), leakage between BAT and VBUS			5	µA
		High-Z Mode, No VBUS, BATFET Disabled (REG09[5] = 1), Battery Monitor Disabled, T_J < 85°C		12	23	µA
		High-Z Mode, No VBUS, BATFET Enabled (REG09[5] = 0), Battery Monitor Disabled, T_J < 85°C		32	60	µA
I_{(VBUS_HIZ)}	Input supply current (VBUS) in buck mode when High-Z mode is enabled	V_(VBUS)= 5 V, High-Z Mode, No Battery, Battery Monitor Disabled		15	35	µA
I_{(VBUS_HIZ)}		V_(VBUS)= 12 V, High-Z Mode, No Battery, Battery Monitor Disabled		25	50	µA
I_(VBUS)	Input supply current (V_BUS) in buck mode	V_BUS > V_(UVLO), V_BUS > V_BAT, Converter not switching		1.5	3	mA
		V_BUS > V_(UVLO), V_BUS > V_BAT, Converter switching, V_BAT = 3.2V, I_SYS = 0A		3		mA
		V_BUS > V_(UVLO), V_BUS > V_BAT, Converter switching, V_BAT = 3.8 V, I_SYS = 0 A		3		mA
I_(BOOST)	Battery discharge current in boost mode	V_BAT = 4.2 V, Boost mode, I_(VBUS)= 0 A, Converter switching		5		mA
VBUS/BAT POWER UP
V_{(VBUS_OP)}	VBUS operating range		3.9		14	V
V_{(VBUS_UVLOZ)}	VBUS for active I²C, no battery		3.6			V
V_(SLEEP)	Sleep mode falling threshold		25	65	120	mV
V_(SLEEPZ)	Sleep mode rising threshold		130	250	370	mV
V_(ACOV)	VBUS over-voltage rising threshold		13.9		14.6	V
V_(ACOV)	VBUS over-voltage falling threshold		13.3		13.9	V
t_{ACOV_RISING}	ACOV rising deglitch	V_VBUS rising		1		µs
t_{ACOV_FALLING}	ACOV falling deglitch	V_VBUS falling		1		ms
V_BAT(UVLOZ)	Battery for active I²C, no VBUS		2.3			V
V_BAT(DPL)	Battery depletion falling threshold		2.15		2.5	V
V_BAT(DPLZ)	Battery depletion rising threshold		2.35		2.7	V
V_(VBUSMIN)	Bad adapter detection threshold			3.8		V
I_(BADSRC)	Bad adapter detection current source			30		mA
POWER-PATH MANAGEMENT
V_SYS	Typical system regulation voltage	I_(SYS) = 0 A, V_BAT> V_SYS(MIN), BATFET Disabled (REG09[5]=1)		V_BAT+ 50 mV		V
V_SYS	Typical system regulation voltage	Isys = 0 A, V_BAT< V_SYS(MIN), BATFET Disabled (REG09[5]=1)		V_SYS(MIN) + 250 mV		V
V_SYS(MIN)	Minimum DC system voltage output	V_BAT< V_SYS(MIN), SYS_MIN = 3.5 V (REG03[3:1] = 101), I_SYS= 0 A	3.60	3.75		V
V_SYS(MAX)	Maximum DC system voltage output	V_BAT = 4.35 V, SYS_MIN = 3.5 V (REG03[3:1] = 101), I_SYS= 0 A		4.40	4.42	V
R_ON(RBFET)	Top reverse blocking MOSFET(RBFET) on-resistance between VBUS and PMID	T_J = -40°C - 85°C		28	40	mΩ
R_ON(RBFET)		T_J = -40°C - 125°C		28	47	mΩ
R_ON(HSFET)	Top switching MOSFET (HSFET) on-resistance between PMID and SW	T_J = -40°C - 85°C		24	33	mΩ
R_ON(HSFET)		T_J = -40°C - 125°C		24	40	mΩ
R_ON(LSFET)	Bottom switching MOSFET (LSFET) on-resistance between SW and GND	T_J = -40°C - 85°C		12	18	mΩ
R_ON(LSFET)		T_J = -40°C - 125°C		12	21	mΩ
V_(FWD)	BATFET forward voltage in supplement mode	BAT discharge current 10 mA		30		mV
BATTERY CHARGER
V_{BAT(REG_RANGE)}	Typical charge voltage range		3.840		4.608	V
V_{BAT(REG_STEP)}	Typical charge voltage step			16		mV
V_BAT(REG)	Charge voltage resolution accuracy	V_BAT = 4.208 V (REG06[7:2] = 010111) or V_BAT = 4.352 V (REG06[7:2] = 100000) T_J = -40°C - 85°C	-0.5%		0.5%
I_{(CHG_REG_RANGE)}	Typical fast charge current regulation range		0		4032	mA
I_{(CHG_REG_STEP)}	Typical fast charge current regulation step			64		mA
I_{(CHG_REG_ACC)}	Fast charge current regulation accuracy	V_BAT= 3.1 V or 3.8 V, I_CHG = 256 mA T_J = -40°C - 85°C	-20%		20%
I_{(CHG_REG_ACC)}	Fast charge current regulation accuracy	V_BAT= 3.1 V or 3.8 V, I_CHG = 1792 mA T_J = -40°C - 85°C	-5%		5%
V_BAT(LOWV)	Battery LOWV falling threshold	Fast charge to precharge, BATLOWV (REG06[1]) = 1	2.6	2.8	2.9	V
	Battery LOWV rising threshold	Precharge to fast charge, BATLOWV (REG06[1]) = 1 (Typical 200-mV hysteresis)	2.8	3.0	3.15	V
	Battery LOWV falling threshold	Fast charge to precharge, BATLOWV (REG06[1]) = 0	2.5	2.6	2.7	V
	Battery LOWV rising threshold	Precharge to fast charge, BATLOWV (REG06[1]) = 0 (Typical 200-mV hysteresis)	2.7	2.8	2.9	V
I_{(PRECHG_RANGE)}	Precharge current range		64		1024	mA
I_{(PRECHG_STEP)}	Typical precharge current step			64		mA
I_{(PRECHG_ACC)}	Precharge current accuracy	V_BAT = 2.6 V, I_PRECHG = 256 mA	–20%		20%
I_{(TERM_RANGE)}	Termination current range		64		1024	mA
I_{(TERM_STEP)}	Typical termination current step			64		mA
I_{(TERM_ACC)}	Termination current accuracy	I_TERM = 256 mA, I_CHG≤ 1344 mA T_J = -20°C - 85°C	-20%		20%
I_{(TERM_ACC)}	Termination current accuracy	I_TERM = 256 mA, I_CHG> 1344 mA T_J = -20°C - 85°C	-20%		20%
V_(SHORT)	Battery short voltage	VBAT falling		2.0		V
V_{(SHORT_HYST)}	Battery short voltage hysteresis	VBAT rising		200		mV
I_(SHORT)	Battery short current	VBAT < 2.2 V		110		mA
V_(RECHG)	Recharge threshold below V_BATREG	V_BAT falling, VRECHG (REG06[0] = 0) = 0		100		mV
V_(RECHG)	Recharge threshold below V_BATREG	V_BAT falling, VRECHG (REG06[0] = 0) = 1		200		mV
I_BAT(LOAD)	Battery discharge load current	V_BAT = 4.2 V	15			mA
I_SYS(LOAD)	System discharge load current	V_SYS = 4.2 V	30			mA
R_ON(BATFET)	SYS-BAT MOSFET (BATFET) on-resistance	T_J = 25°C		5	7	mΩ
R_ON(BATFET)	SYS-BAT MOSFET (BATFET) on-resistance	T_J = -40°C - 125°C		5	10	mΩ
R_BATSEN	BATSEN input resistance			800		kΩ
INPUT VOLTAGE / CURRENT REGULATION
V_{IN(DPM_RANGE)}	Typical input voltage regulation range		3.9		15.3	V
V_{IN(DPM_STEP)}	Typical input voltage regulation step			100		mV
V_{IN(DPM_ACC)}	Input voltage regulation accuracy	VINDPM = 4.4 V, 7.8 V, 10.8 V	-3%		3%
I_{IN(DPM_RANGE)}	Typical input current regulation range		100		3250	mA
I_{IN(DPM_STEP)}	Typical input current regulation step			50		mA
I_{IN(DPM100_ACC)}	Input current 100mA regulation accuracy V_BAT = 5V, current pulled from SW	IINLIM (REG00[5:0]) = 100 mA	85	90	100	mA
I_{IN(DPM_ACC)}	Input current regulation accuracy V_BAT = 5V, current pulled from SW	USB150, IINLIM (REG00[5:0]) = 150 mA	125	135	150	mA
		USB500, IINLIM (REG00[5:0]) = 500 mA	440	470	500	mA
		USB900, IINLIM (REG00[5:0]) = 900 mA	750	825	900	mA
		Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA	1300	1400	1500	mA
I_IN(START)	Input current regulation during system start up	V_SYS = 2.2 V, IINLIM (REG00[5:0]) ≥ 200 mA			200	mA
K_ILIM		I_INMAX = K_ILIM/R_ILIM, Input Current regulation by ILIM pin = 1.5 A	290	320	350	A x Ω
VOK (bq25898)/DSEL (bq25898D)
V_{VOK_OH}	Voltage	VBUS > 6 V I(VOK) = 20 mA and I(REGN) = 30 mA	4.75		5.25	V
V_{VOK_OH}	Voltage	VBUS = 5 V I(VOK) = 5 mA and I(REGN) = 30 mA	4.35		4.8	V
V_{VOK_OL}	Voltage	Battery only VBAT = 3.8 V, I(VOK) = -10 mA			0.4	V
V_{DSEL_OH}	Voltage	I(DSEL) = 20 mA and I(REGN) = 30 mA, VBUS = 5 V	1.3			V
V_{DSEL_OL}	Voltage	I(DSEL) = -10 mA and I(REGN) = 30 mA, VBUS = 5 V			0.4	V
D+/D- DETECTION (bq25898D)
I_{(10UA_ISRC)}	D+ connection check current source		7	10	14	µA
I_{(100UA_ISINK)}	D+/D- current sink (100 µA)		50	100	150	µA
I_{(DPDM_LKG)}	D+/D- Leakage current	D–, switch open	–1		1	µA
I_{(DPDM_LKG)}	D+/D- Leakage current	D+, switch open	–1		1	µA
I_{(1P6MA_ISINK)}	D+/D- current sink (1.6 mA)		1.35	1.60	1.75	mA
R_{(D–_DWN)}	D– pulldown for connection check		14.25		24.8	kΩ
V_{FLOAT_VDPSRC}	D+/D- Voltage source (HIZ)	REG01[7:5] = 000 (default) or REG01[4:2] = 000 (default)		HIZ		V
V_{0P0_VDSRC}	D+/D- Voltage source (0 V)	REG01[7:5] = 001 or REG01[4:2] = 001	0		0.15	V
V_{0P6_VDSRC}	D+/D- Voltage source (0.6 V)	REG01[7:5] = 010 or REG01[4:2] = 010	0.5	0.6	0.7	V
V_{1P2_DPVSRC}	D+/D- Voltage source (1.2 V)	REG01[7:5] = 011 or REG01[4:2] = 011	1.075	1.2	1.325	V
V_{2P0_DPVSRC}	D+/D- Voltage source (2.0 V)	REG01[7:5] = 100 or REG01[4:2] = 100	1.875	2	2.125	V
V_{2P7_DPVSRC}	D+/D- Voltage source (2.7 V)	REG01[7:5] = 101 or REG01[4:2] = 101	2.575	2.7	2.825	V
V_{3P3_DPVSRC}	D+/D- Voltage source (3.3 V)	REG01[7:5] = 110 or REG01[4:2] = 110 or REG01[4:2] = 111	3.15	3.3	3.45	V
R_{DPDM_SHORT}	D+/D- Short REG01[7:5] = 111				200	Ω
V_{(0P4_VTH)}	D+/D- low comparator threshold		250		400	mV
V_{(0P8_VTH)}	D+ low comparator threshold				0.8	V
V_{(2P7_VTH)}	D+/D- comparator threshold for non-standard adapter detection (Divider 1, 3,or 4)		2.55		2.85	V
V_{(2P0_VTH)}	D+/D- comparator threshold for non-standard adapter detection (Divider 1, 3)		1.85		2.15	V
V_{(1P2_VTH)}	D+/D- comparator threshold for non-standard adapter detection (Divider 2)		1.05		1.35	V
BAT OVER-VOLTAGE/CURRENT PROTECTION
V_BAT(OVP)	Battery over-voltage threshold	V_BAT rising, as percentage of V_BAT(REG)		104%
V_{BAT(OVP_HYST)}	Battery over-voltage hysteresis	V_BAT falling, as percentage of V_BAT(REG)		2%
I_{BAT(FET_OCP)}	System over-current threshold		9			A
THERMAL REGULATION AND THERMAL SHUTDOWN
T_REG	Junction temperature regulation accuracy	REG08[1:0] = 11		120		°C
T_SHUT	Thermal shutdown rising temperature	Temperature rising		160		°C
T_SHUT(HYS)	Thermal shutdown hysteresis	Temperature falling		30		°C
JEITA THERMISTOR COMPARATOR (BUCK MODE)
V_(T1)	T1 (0°C) threshold, charge suspended T1 below this temperature.	As percentage to V_(REGN)	72.75%	73.25%	73.75%
V_{(T1_HYS)}	Charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) above this temperature.	As Percentage to V_(REGN)		1.4%
V_(T2)	T2 (10°C) threshold, charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2]) below this temperature.	As Percentage to V_(REGN)	67.75%	68.25%	68.75%
V_{(T2_HYS)}	Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) above this temperature.	As Percentage to V_(REGN)		1.4%
V_(T3)	T3 (45°C) threshold,charge back to ICHG (REG04[6:0]) and VREG-200mV (REG06[7:2]) above this temperature.	As percentage to V_(REGN)	44.25v	44.75%	45.25%
V_{(T3_HYS)}	Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2]) below this temperature.	As Percentage to V_(REGN)		1%
V_(T5)	T5 (60°C) threshold, charge suspended above this temperature.	As Percentage to V_(REGN)	33.875%	34.375%	34.875%
V_{(T5_HYS)}	Charge back to ICHG (REG04[6:0]) and VREG-200mV (REG06[7:2]) below this temperature.	As Percentage to V_(REGN)		1.25%
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
V_(BCOLD1)	Cold temperature threshold 1, TS pin voltage rising threshold	As percentage to V_REGN REG01[5] = 1 (Approx. -20°C w/ 103AT)	79.5%	80%	80.5%
V_{(BCOLD1_HYS)}	Cold temperature threshold 1, TS pin voltage falling threshold	As percentage to V_REGN REG01[5] = 1		1%
V_(BHOT2)	Hot temperature threshold 2, TS pin voltage falling threshold	As percentage to V_REGN REG01[7:6] = 10 (Approx. 65°C w/ 103AT)	30.75%	31.25%	31.75%
V_{(BHOT2_HYS)}	Hot temperature threshold 2, TS pin voltage rising threshold	As percentage to V_REGN REG01[7:6] = 10		3%
PWM
F_SW	PWM switching frequency, and digital clock	Oscillator frequency	1.32		1.68	MHz
D_MAX	Maximum PWM duty cycle			97%
BOOST MODE OPERATION
V_{(OTG_REG_RANGE)}	Typical boost mode regulation voltage range		4.55		5.55	V
V_{(OTG_REG_STEP)}	Typical boost Mode Regulation voltage step			64		mV
V_{(OTG_REG_ACC)}	Boost mode regulation voltage accuracy	I(VBUS) = 0 A, BOOSTV = 4.998 V (REG0A[7:4] = 0111)	-3%		3%
V_{(OTG_BAT)}	Battery voltage exiting boost mode	BAT falling, REG03[0] = 0	2.7		2.9	V
V_{(OTG_BAT)}	Battery voltage exiting boost mode	BAT falling, REG03[0] = 1	2.4		2.6	V
I_(OTG)	Typical boost mode output current range		0.5		2.45	A
I_{(OTG_OCP_ACC)}	Boost mode RBFET over-current protection accuracy	BOOST_LIM = 1.5 A (REG0A[2:0] = 100)	1.5		2.0	A
V_{(OTG_OVP)}	Boost mode over-voltage threshold	Rising threshold	5.8	6		V
REGN LDO
V_(REGN)	REGN LDO output voltage	V_(VBUS) = 9 V, I_(REGN) = 40 mA	5.6	6	6.4	V
V_(REGN)	REGN LDO output voltage	V_(VBUS) = 5 V, I_(REGN) = 20 mA	4.7	4.8		V
I_(REGN)	REGN LDO current limit	V_(VBUS) = 9 V, V_(REGN) = 3.8 V	50			mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES	Resolution	Rising threshold		7		bits
V_BAT(RANGE)	Typical battery voltage range	V_(VBUS) > V_BAT + V_(SLEEP) or OTG mode is enabled	2.304		4.848	V
V_BAT(RANGE)	Typical battery voltage range	V_(VBUS) < V_BAT + V_(SLEEP) and OTG mode is disabled	V_{SYS_MIN}		4.848	V
V_{(BAT_RES)}	Typical battery voltage resolution			20		mV
V_{(SYS_RANGE)}	Typical system voltage range	V_(VBUS) > V_BAT + V_(SLEEP) or OTG mode is enabled	2.304		4.848	V
V_{(SYS_RANGE)}	Typical system voltage range	V_(VBUS) < V_BAT + V_(SLEEP) and OTG mode is disabled	V_{SYS_MIN}		4.848	V
V_{(SYS_RES)}	Typical system voltage resolution			20		mV
V_{(VBUS_RANGE)}	Typical V_VBUS voltage range	V_(VBUS) > V_BAT + V_(SLEEP) or OTG mode is enabled	2.6		15.3	V
V_{(VBUS_RES)}	Typical V_VBUS voltage resolution			100		mV
I_BAT(RANGE)	Typical battery charge current range	V_(VBUS) > V_BAT + V_(SLEEP) and V_BAT > V_BAT(SHORT)	0		4.032	A
I_BAT(RES)	Typical battery charge current resolution			50		mA
V_{(TS_RANGE)}	Typical TS voltage range		21%		80%
V_{(TS_RES)}	Typical TS voltage resolution			0.47%
LOGIC I/O PIN (OTG, CE, PSEL, QON)
V_IH	Input high threshold level		1.3			V
V_IL	Input low threshold level				0.4	V
I_IN(BIAS)	High level leakage current	Pull-up rail 1.8 V			1	µA
V_(QON)	Internal /QON pull-up	Battery only mode		BAT		V
		V_(VBUS) = 9 V		5.8		V
		V_(VBUS) = 5 V		4.3		V
R_(QON)	Internal /QON pull-up resistance			200		kΩ
LOGIC I/O PIN (INT, STAT, PG)
V_OL	Output low threshold level	Sink Current = 5 mA, Sink current			0.4	V
I_{OUT_BIAS}	High level leakage current	Pull-up rail 1.8 V			1	µA
I2C INTERFACE (SCL, SDA)
V_IH	Input high threshold level, SCL and SDA	Pull-up rail 1.8 V	1.3			V
V_IL	Input low threshold level	Pull-up rail 1.8 V			0.4	V
V_OL	Output low threshold level	Sink Current = 5 mA, Sink current			0.4	V
I_BIAS	High level leakage current	Pull-up rail 1.8 V			1	µA

8.6 Timing Requirements

			MIN	NOM	MAX	UNIT
VBUS/BAT POWER UP
t_BADSRC	Bad adapter detection duration			30		msec
BAT OVER-VOLTAGE PROTECTION
t_BATOVP	Battery over-voltage deglitch time to disable charge			1		µs
BATTERY CHARGER
t_RECHG	Recharge deglitch time			20		msec
Current Pulse Control
t_{PUMPX_STOP}	Current pulse control stop pulse		430		570	msec
t_{PUMPX_ON1}	Current pulse control long on pulse		240		360	msec
t_{PUMPX_ON2}	Current pulse control short on pulse		70		130	msec
t_{PUMPX_OFF}	Current pulse control off pulse		70		130	msec
t_{PUMPX_DLY}	Current pulse control stop start delay		80		225	msec
BATTERY MONITOR
t_CONV	Conversion time	CONV_RATE(REG02[6]) = 0		8	1000	msec
QON and SHIPMODE TIMING
t_SHIPMODE	QON low time to turn on BATFET and exit ship mode	T_J = -10°C - 60°C	0.8		1.3	sec
t_{QON_RST}	QON low time to enable full system reset	T_J = -10°C - 60°C	15.5		23	sec
t_{BATFET_RST}	BATFET off time during full system reset	T_J= -10°C - 60°C	250		400	msec
t_{SM_DLY}	Enter ship mode delay	T_J = -10°C - 60°C	10		15	sec
I2C INTERFACE
f_SCL	SCL clock frequency				400	KHz
DIGITAL CLOCK and WATCHDOG TIMER
f_LPDIG	Digital low power clock	REGN LDO disabled	18	30	45	KHz
f_DIG	Digital clock	REGN LDO enabled	1320	1500	1680	KHz
t_WDT	Watchdog reset time	WATCHDOG (REG07[5:4])=11, REGN LDO disabled	100	160		sec
t_WDT	Watchdog reset time	WATCHDOG (REG07[5:4])=11, REGN LDO enabled	136	160		sec