ZHCSIK0A July 2018 – October 2021 TPS3430
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DRC|10
訂購信息
8.2.1.2.3 Calculating the WDO Pull-up Resistor - Design 1
Figure 8-7 shows the TPS3430 uses an open-drain configuration for the WDO circuit. When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pull-up resistor, there are three key specifications to keep in mind: the pull-up voltage (VPU), the recommended maximum WDO pin current (IWDO), and VOL. The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.4 V with IWDO kept below 10 mA. For this example, with a VPU of 3.3 V, a resistor must be chosen to keep IWDO below 200 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pull-up resistor value of 16.5 kΩ is selected, which sinks a maximum of 200 μA when WDO is asserted. WDO current is at 200 μA and the low-level output voltage is approximately zero.
Figure 8-7 Open-Drain
WDO Configuration