PGA116

正在供貨

具有 10 通道多路復(fù)用器的零漂移、100μV 偏移電壓、12nV/√Hz 噪聲、RRO（二進(jìn)制增益）可編程增益放大器

產(chǎn)品詳情

PGA/VGA PGA Number of channels 10 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (μV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 42 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (μV√Hz) 0.012 Slew rate (typ) (V/μs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
PGA/VGA PGA Number of channels 10 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (μV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 42 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (μV√Hz) 0.012 Slew rate (typ) (V/μs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 20 41.6 mm2 6.5 x 6.4
  • Rail-to-Rail Input and Output
  • Offset: 25 μV (Typical), 100 μV
    (Maximum)
  • Zer? Drift: 0.35 μV/°C (Typical), 1.2 μV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 μA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI? Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 μV (Typical), 100 μV
    (Maximum)
  • Zer? Drift: 0.35 μV/°C (Typical), 1.2 μV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 μA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI? Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
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PGA117 正在供貨 具有 10 通道多路復(fù)用器的零溫漂、100μV 失調(diào)電壓、12nV/√Hz 噪聲、RRO（范圍增益）可編程增益放大器 This device offers scope gains 1, 2, 5, 10, 20, 50, 100, 200 instead of binary gains
功能與比較器件相同，但引腳排列有所不同
PGA112 正在供貨 具有 2 通道多路復(fù)用器的零溫漂、100μV 失調(diào)電壓、12nV/√Hz 噪聲、RRO（二進(jìn)制增益）可編程增益放大器 This device offers 2 channel mux instead of 10 channel mux.
PGA113 正在供貨 具有 2 通道多路復(fù)用器的零溫漂、100μV 失調(diào)電壓、12nV/√Hz 噪聲、RRO（范圍增益）可編程增益放大器 This device offers 2 channel mux instead of 10 channel mux, and scope gains instead of binary gains.

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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 PGA11x Zer?-Drift Programmable Gain Amplifier With Mux 數(shù)據(jù)表 (Rev. C) PDF | HTML 2015年 11月 30日
應(yīng)用手冊 所選封裝材料的熱學(xué)和電學(xué)性質(zhì) 2008年 10月 16日

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TINA-TI 提供了 SPICE 所有的傳統(tǒng)直流、瞬態(tài)和頻域分析以及更多。TINA 具有廣泛的后處理功能，允許您按照希望的方式設(shè)置結(jié)果的格式。虛擬儀器允許您選擇輸入波形、探針電路節(jié)點(diǎn)電壓和波形。TINA 的原理圖捕獲非常直觀 - 真正的“快速入門”。

TINA-TI 安裝需要大約 500MB。直接安裝，如果想卸載也很容易。我們相信您肯定會愛不釋手。

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參考設(shè)計(jì)

TIDA-00191 — 具有增強(qiáng)的電流范圍的電機(jī)電子過載繼電器模擬前端

此參考設(shè)計(jì)是電子過載繼電器的模擬前端 (AFE)，用于監(jiān)視和保護(hù)電機(jī)不受過流或欠流事件的損害。如果開發(fā)人員需要為工業(yè)應(yīng)用中的靈敏交流電機(jī)設(shè)計(jì)過載繼電器，那么此工具便是其理想選擇。這種基于可編程增益放大器 (PGA) 的模擬前端旨在作為簡單的評估平臺，可實(shí)現(xiàn)準(zhǔn)確的、行業(yè)領(lǐng)先的 10:1 全載電流 (FLA) 范圍，并且可在 -10 至 +70°C 溫度范圍內(nèi)重復(fù)。
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原理圖: PDF
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TSSOP (PW) 20 Ultra Librarian

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包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
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  • 制造廠地點(diǎn)
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