SN74CBT3125C

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具有 –2V 下沖保護(hù)的 5V、1:1 (SPST)、4 通道 FET 總線開關(guān)

產(chǎn)品詳情

Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 5.5 Ron (typ) (mΩ) 3000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 12.5 OFF-state leakage current (max) (μA) 10 Ron (max) (mΩ) 12000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 5.5 Ron (typ) (mΩ) 3000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 12.5 OFF-state leakage current (max) (μA) 10 Ron (max) (mΩ) 12000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
SOIC (D) 14 51.9 mm2 8.65 x 6 SSOP (DB) 14 48.36 mm2 6.2 x 7.8 SSOP (DBQ) 16 29.4 mm2 4.9 x 6 TSSOP (PW) 14 32 mm2 5 x 6.4 VQFN (RGY) 14 12.25 mm2 3.5 x 3.5
  • Undershoot Protection for Off-Isolation on A and B Ports Up To –2 V
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low On-State Resistance (ron) Characteristics
          (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion
         (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption
         (ICC = 3 μA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Bus Isolation, Low-Distortion Signal Gating
  • Undershoot Protection for Off-Isolation on A and B Ports Up To –2 V
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low On-State Resistance (ron) Characteristics
          (ron = 3 Typical)
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion
         (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption
         (ICC = 3 μA Max)
  • VCC Operating Range From 4 V to 5.5 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Bus Isolation, Low-Distortion Signal Gating

The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3125C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3125C is organized as four 1-bit bus switches with separate output-enable (1OE\, 2OE\, 3OE\, 4OE\) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE\ is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBT3125C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT3125C provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

The SN74CBT3125C is organized as four 1-bit bus switches with separate output-enable (1OE\, 2OE\, 3OE\, 4OE\) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE\ is low, the associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 SN74CBT3125C 數(shù)據(jù)表 (Rev. A) 2003年 10月 15日
應(yīng)用手冊(cè) 選擇正確的德州儀器 (TI) 信號(hào)開關(guān) (Rev. E) PDF | HTML 英語版 (Rev.E) PDF | HTML 2022年 8月 5日
應(yīng)用手冊(cè) CBT-C、CB3T 和 CB3Q 信號(hào)開關(guān)系列 (Rev. C) PDF | HTML 英語版 (Rev.C) PDF | HTML 2022年 3月 11日
應(yīng)用手冊(cè) 多路復(fù)用器和信號(hào)開關(guān)詞匯表 (Rev. B) 英語版 (Rev.B) PDF | HTML 2022年 3月 11日
應(yīng)用簡(jiǎn)報(bào) 利用關(guān)斷保護(hù)信號(hào)開關(guān)消除電源時(shí)序 (Rev. C) 英語版 (Rev.C) PDF | HTML 2021年 10月 21日
選擇指南 Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AB) 2014年 11月 17日
選擇指南 小尺寸邏輯器件指南 (Rev. E) 最新英語版本 (Rev.G) 2012年 7月 16日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
更多文獻(xiàn)資料 Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
應(yīng)用手冊(cè) Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
應(yīng)用手冊(cè) Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日

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用戶指南: PDF
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仿真模型

SN74CBT3125C HSPICE Model (Rev. A)

SCDJ018A.ZIP (62 KB) - HSpice Model
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仿真模型

SN74CBT3125C IBIS Model

SCDM046.ZIP (27 KB) - IBIS Model
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封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SOIC (D) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
SSOP (DBQ) 16 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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