產(chǎn)品詳情

Sampling rate (max) (kHz) 192 Control interface I2C Architecture Class-D Operating temperature range (°C) -40 to 85 Rating Catalog
Sampling rate (max) (kHz) 192 Control interface I2C Architecture Class-D Operating temperature range (°C) -40 to 85 Rating Catalog
VQFN (RHB) 32 25 mm2 5 x 5
  • Stereo Audio DAC with 95-dB SNR
  • Supports 8-kHz to 192-kHz Sample Rates
  • Mono Class-D BTL Speaker Driver (2.5 W Into 4-Ω or 1.6 W Into 8-Ω)
  • Two Single-Ended Inputs With Mixing and Output Level Control
  • Stereo Headphone/Lineout and Mono Class-D Speaker Outputs Available
  • Microphone Bias
  • Headphone Detection
  • 25 Built-in Digital Audio Processing Blocks (PRB_P1 – PRB_P25) Providing Biquad and FIR Filters, DRC, and 3-D Structures
  • Digital Mixing Capability
  • Pin Control or Register Control for Digital-Playback Volume-Control Settings
  • Digital Sine-Wave Generator for Beeps and Key Clicks (PRB_P25)
  • Programmable PLL for Flexible Clock Generation
  • I2S, Left-Justified, Right-Justified, DSP, and TDM Audio Interfaces
  • I2C Control With Register Auto-Increment
  • Full Power-Down Control
  • Power Supplies:
    • Analog: 2.7 V–3.6 V
    • Digital Core: 1.65 V–1.95 V
    • Digital I/O: 1.1 V–3.6 V
    • Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)
  • 5-mm × 5-mm 32-VQFN Package
  • Stereo Audio DAC with 95-dB SNR
  • Supports 8-kHz to 192-kHz Sample Rates
  • Mono Class-D BTL Speaker Driver (2.5 W Into 4-Ω or 1.6 W Into 8-Ω)
  • Two Single-Ended Inputs With Mixing and Output Level Control
  • Stereo Headphone/Lineout and Mono Class-D Speaker Outputs Available
  • Microphone Bias
  • Headphone Detection
  • 25 Built-in Digital Audio Processing Blocks (PRB_P1 – PRB_P25) Providing Biquad and FIR Filters, DRC, and 3-D Structures
  • Digital Mixing Capability
  • Pin Control or Register Control for Digital-Playback Volume-Control Settings
  • Digital Sine-Wave Generator for Beeps and Key Clicks (PRB_P25)
  • Programmable PLL for Flexible Clock Generation
  • I2S, Left-Justified, Right-Justified, DSP, and TDM Audio Interfaces
  • I2C Control With Register Auto-Increment
  • Full Power-Down Control
  • Power Supplies:
    • Analog: 2.7 V–3.6 V
    • Digital Core: 1.65 V–1.95 V
    • Digital I/O: 1.1 V–3.6 V
    • Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)
  • 5-mm × 5-mm 32-VQFN Package

The TLV320DAC3100 device is a low-power, highly integrated, high-performance stereo audio DAC with 24-bit stereo playback and digital audio processing blocks.

The device integrates headphone drivers and speaker drivers. The mono speaker driver can drive loads down to 4 Ω. The TLV320DAC3100 device has a suite of built-in processing blocks for digital audio processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ can be supported by the programmable digital signal-processing block. An on-chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be controlled either by pin control or by register control. The audio functions are controlled using the I2C serial bus.

The TLV320DAC3100 device has a programmable digital sine-wave generator and is available in a 32-pin VQFN package.

The TLV320DAC3100 device is a low-power, highly integrated, high-performance stereo audio DAC with 24-bit stereo playback and digital audio processing blocks.

The device integrates headphone drivers and speaker drivers. The mono speaker driver can drive loads down to 4 Ω. The TLV320DAC3100 device has a suite of built-in processing blocks for digital audio processing. The digital audio data format is programmable to work with popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or EQ can be supported by the programmable digital signal-processing block. An on-chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be controlled either by pin control or by register control. The audio functions are controlled using the I2C serial bus.

The TLV320DAC3100 device has a programmable digital sine-wave generator and is available in a 32-pin VQFN package.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 TLV320DAC3100 Low-Power Stereo Audio DAC With Audio Processing and Mono Class-D Speaker Amplifier 數(shù)據(jù)表 (Rev. C) PDF | HTML 2017年 1月 24日
應(yīng)用手冊(cè) Audio Serial Interface Configurations for Audio Codecs (Rev. A) 2019年 6月 27日
應(yīng)用手冊(cè) PLL and Clocking Configuration for Audio Devices PDF | HTML 2019年 3月 26日
應(yīng)用手冊(cè) TLV320AIC31xx and TLV320DAC31xx Power Consumption Characterization (Rev. B) 2014年 9月 3日
應(yīng)用手冊(cè) TLV320DAC3100 Open Load Detection Test (Rev. B) 2013年 7月 27日
應(yīng)用手冊(cè) TLV320DAC3100 Open Load Detection Test (Rev. A) 2013年 4月 26日
應(yīng)用手冊(cè) Coefficient RAM Access Mechanisms.. (Rev. D) 2012年 1月 25日
應(yīng)用手冊(cè) Audio Serial Interface Configurations for Audio Codecs 2010年 9月 22日
應(yīng)用手冊(cè) Interfacing an I2S Device to an MSP430 Device (Rev. A) 2010年 3月 22日
EVM 用戶指南 ACEV-1A EVM User's Guide 2009年 12月 17日

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評(píng)估板

TLV320DAC3100EVM-U — TLV320DAC3100EVM-U 評(píng)估模塊

TLV320DAC3100EVM-U (ACEV-1A) 是用于 TLV320DAC3100 音頻編解碼器的完整評(píng)估模塊。

此 EVM 受 TI 的 CodecControl 軟件支持，該軟件是用于 TI 音頻編解碼器的基于方框圖的圖形用戶界面。

TLV320DAC3100EVM-U 可連接到 PC 上的 USB 端口。USB 接口可以為 EVM 提供電源、控制和音頻流數(shù)據(jù)。該 EVM 具有外部控制信號(hào)和數(shù)字音頻數(shù)據(jù)的連接，便于進(jìn)行高級(jí)操作。

用戶指南: PDF
TI.com 上無現(xiàn)貨
驅(qū)動(dòng)程序或庫

TLV320DAC31XX-DRIVERS — TLV320DAC31XX DAC 系列 Linux 驅(qū)動(dòng)程序支持

這些 Linux 驅(qū)動(dòng)程序支持用于 TLV320DAC31xx 器件系列的低功耗音頻數(shù)模轉(zhuǎn)換器 (DAC)，并且包括 .c 和 .h 文件。點(diǎn)擊下方的“Go to third party”按鈕將轉(zhuǎn)到 git.kernal.org，您可從中下載相應(yīng)的驅(qū)動(dòng)程序。

Linux 主線狀態(tài)
Linux 主線中提供：是
可通過 git.ti.com 獲?。翰贿m用

其他文件：
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仿真模型

TLV320DAC3100 IBIS Model

SLAM190.ZIP (51 KB) - IBIS Model
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模擬工具

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