產(chǎn)品詳情

DSP type 1 C54x DSP (max) (MHz) 50 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 100
DSP type 1 C54x DSP (max) (MHz) 50 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 100
LQFP (PGE) 144 484 mm2 22 x 22
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus-Holder Feature
  • Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
  • 4K x 16-Bit On-Chip ROM
  • 8K x 16-Bit Dual-Access On-Chip RAM
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Efficient Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank Switching
    • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 20-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS) for 3.3-V Power Supply (1.8-V Core)
  • 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 144-Ball MicroStar BGA? (GGU Suffix)

IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus-Holder Feature
  • Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
  • 4K x 16-Bit On-Chip ROM
  • 8K x 16-Bit Dual-Access On-Chip RAM
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Efficient Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank Switching
    • On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 20-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS) for 3.3-V Power Supply (1.8-V Core)
  • 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 144-Ball MicroStar BGA? (GGU Suffix)

IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners

The TMS320VC5401 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

The TMS320VC5401 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 TMS320VC5401 Fixed-Point Digital Signal Processor 數(shù)據(jù)表 (Rev. D) 2008年 10月 17日
* 勘誤表 TMS320VC5401 Silicon Errata 2001年 7月 31日
用戶指南 TMS320C54x Chip Support Library API Reference Guide (Rev. D) 2003年 5月 5日
用戶指南 TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) 2001年 3月 31日
用戶指南 TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) 2001年 1月 31日
用戶指南 TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) 2001年 1月 31日
用戶指南 TMS320C54x DSP Applications Guide Reference Set Volume 4 1996年 10月 1日

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調(diào)試探針

TMDSEMU560V2STM-U — XDS560? 軟件 v2 系統(tǒng)跟蹤 USB 調(diào)試探針

XDS560v2 是 XDS560™ 系列調(diào)試探針中性能非常出色的產(chǎn)品，同時支持傳統(tǒng) JTAG 標(biāo)準(zhǔn) (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，它不支持串行線調(diào)試 (SWD)。

所有 XDS 調(diào)試探針在所有具有嵌入式跟蹤緩沖器 (ETB) 的 ARM 和 DSP 處理器中均支持內(nèi)核和系統(tǒng)跟蹤。對于引腳上的跟蹤，需要 XDS560v2 PRO TRACE。

XDS560v2 通過 MIPI HSPT 60 引腳連接器（帶有多個用于 TI 14 引腳、TI 20 引腳和 ARM 20 引腳的適配器）連接到目標(biāo)板，并通過 USB2.0 高速 (480Mbps) (...)

TI.com 上無現(xiàn)貨
調(diào)試探針

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系統(tǒng)跟蹤 USB 和以太網(wǎng)

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 處理器調(diào)試探針（仿真器）的第一種型號。XDS560v2 是 XDS 系列調(diào)試探針中性能最高的一款，同時支持傳統(tǒng) JTAG 標(biāo)準(zhǔn) (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存儲器緩沖區(qū)中加入了系統(tǒng)引腳跟蹤。這種外部存儲器緩沖區(qū)適用于指定的 TI 器件，通過捕獲相關(guān)器件級信息，獲得準(zhǔn)確的總線性能活動和吞吐量，并對內(nèi)核和外設(shè)進(jìn)行電源管理。此外，對于帶有嵌入式緩沖跟蹤器 (ETB) 的所有 ARM 和 DSP 處理器，所有 XDS (...)

TI.com 上無現(xiàn)貨
調(diào)試探針

LB-3P-TRACE32-DSP — 適用于數(shù)字信號處理器 (DSP) 的 Lauterbach TRACE32 調(diào)試和跟蹤系統(tǒng)

Lauterbach‘s TRACE32? tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

來源：Lauterbach GmbH
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仿真模型

C5401 GGU BSDL Model

SPRM170.ZIP (5 KB) - BSDL Model
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仿真模型

C5401 PGE BSDL Model

SPRM169.ZIP (5 KB) - BSDL Model
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封裝 引腳 CAD 符號、封裝和 3D 模型
LQFP (PGE) 144 Ultra Librarian

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  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
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