ZHCSI83C may 2018 – may 2023 ADC12DL3200
PRODUCTION DATA
A user-defined test pattern mode allows the user to define a pattern to meet various system needs. Example patterns included strobe patterns to look for inter-symbol interference issues, single-bit patterns to verify TX to RX lane connections, and multi-bit patterns to verify time alignment. The pattern is up to eight samples long and is programmed using the UPAT0 through UPAT7 registers. The user pattern repeats at the beginning of each frame. If the frame length is less than eight samples than the user pattern is truncated. If the frame length is greater than eight samples then the user pattern repeats until the end of the frame.
Additionally, there are controls to invert specific bits of the user-defined pattern for each of the LVDS buses in order to allow a unique pattern on each bus. UPAT_INV_x (x = A, B, C, or D) in the UPAT_CTRL register, as shown in Table 7-16, inverts the specified bit in each LVDS bus when set to 1. The inversion is independent of the other buses.
| REGISTER CONTROL | LVDS BUS AFFECTED | LVDS BUS BIT INVERTED | BUS INVERSION MASK |
|---|---|---|---|
| UPAT_INV_A | A | 8 | 0001 0000 0000 |
| UPAT_INV_B | B | 9 | 0010 0000 0000 |
| UPAT_INV_C | C | 10 | 0100 0000 0000 |
| UPAT_INV_D | D | 11 | 1000 0000 0000 |
A predefined pattern can also be selected by setting LANE_PAT in the UPAT_CTRL register to 1. LANE_PAT automatically overrides the programmed user pattern. LANE_PAT is a fixed eight sample sequence output on each LVDS bus. The pattern is 0x000, 0xFFF, 0x000, 0x000, 0x000, 0xFFF, 0xFFF, and 0xFFF. The repetition rules regarding frame length defined for the user pattern apply to the lane pattern as well.