ZHCSMJ1 October 2021 LM61430-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 EN/SYNC Uses for Enable and VIN UVLO
- 8.3.2 EN/SYNC Pin Uses for Synchronization
- 8.3.3 Clock Locking
- 8.3.4 Adjustable Switching Frequency
- 8.3.5 PGOOD Output Operation
- 8.3.6 Internal LDO, VCC UVLO, and BIAS Input
- 8.3.7 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
- 8.3.8 Adjustable SW Node Slew Rate
- 8.3.9 Spread Spectrum
- 8.3.10 Soft Start and Recovery From Dropout
- 8.3.11 Output Voltage Setting
- 8.3.12 Overcurrent and Short Circuit Protection
- 8.3.13 Thermal Shutdown
- 8.3.14 Input Supply Current
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.1 EN/SYNC Uses for Enable and VIN UVLO
Start-up and shutdown are controlled by the EN/SYNC input and VIN UVLO. For the device to remain in shutdown mode, apply a voltage below VEN_WAKE (0.4 V) to the EN/SYNC pin. In shutdown mode, the quiescent current drops to 0.6 μA (typical). At a voltage above VEN_WAKE and below VEN, VCC is active and the SW node is inactive. Once the EN voltage is above VEN, the chip begins to switch normally provided the input voltage is above 3 V.
The EN/SYNC pin cannot be left floating. The simplest way to enable the operation is to connect the EN/SYNC pin to VIN, which allows self-start-up of the LM61430-Q1 when VIN drives the internal VCC above its UVLO level. However, many applications benefit from the employment of an enable divider network as shown in Figure 8-1, which establishes a precision input undervoltage lockout (UVLO). This can be used for sequencing, to prevent re-triggering the device when used with long input cables, or to reduce the occurrence of deep discharge of a battery power source. Note that the precision enable threshold VEN has a 5% tolerance. Hysteresis must be enough to prevent re-triggering. External logic output of another IC can also be used to drive the EN/SYNC pin, allowing system power sequencing.
Figure 8-1 VIN UVLO Using the EN pinResistor values can be calculated using Equation 1. See Section 9.2.2.11 for additional information.
where
- VON = Desired typical start-up input voltage for the circuit being designed
Note that since the EN/SYNC pin can also be used as an external synchronization clock input. A blanking time, tB, is applied to the enable logic after a clock edge is detected. Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in shutdown mode. The blanking time ranges from 4 μs to 28 μs. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 μs.