ZHCSQI8O December 1997 – May 2022 SN74LV125A
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.
These devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.