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ZHCSH20 October 2017 TAS5634

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DDV|44
- MPDS169G

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DDV|44
- PPTD233A

訂購信息

6 Pin Configuration and Functions

The TAS5634 is available in a thermally-enhanced, 44-Pin HTSSOP package (DDV).

The package contains a PowerPAD™ that is located on the top side of the device for convenient thermal coupling to a heatsink.

DDV Package

44 Pin (HTSSOP)

Top View

Pin Functions

PIN		I/O/P⁽¹⁾	DESCRIPTION	Sections
NAME	NO.	I/O/P⁽¹⁾	DESCRIPTION	Sections
AVDD	13	P	Analog internal voltage regulator output. Place 1 μF capacitor to GND.
BST_A	44	P	Bootstrap pin, A-side. Connect 0.33 nF ceramic capacitor to OUT_A.
BST_B	43	P	Bootstrap pin, B-side. Connect 0.33 nF ceramic capacitor to OUT_B.
BST_C	24	P	Bootstrap pin, C-side. Connect 0.33 nF ceramic capacitor to OUT_C.
BST_D	23	P	Bootstrap pin, D-side. Connect 0.33 nF ceramic capacitor to OUT_D.
CLIP	18	O	Clipping warning; open drain; active low. Connect 10 kΩ pull-up resistor to DVDD to monitor. If unused, do not connect.
C_START	7	O	Startup ramp timing control pin. Connect capacitor to ground. 330nF for BTL / PBTL mode. 1 μF for SE mode.
DVDD	8	P	Digital internal voltage regulator output. Place 1 μF capacitor to GND.
FAULT	16	O	Fault signal output, open drain; active low. Connect 10 kΩ pull-up resistor to DVDD to monitor. If unused, do not connect.
GND	9, 10, 11, 12, 25, 26, 33, 34, 41, 42	P	Ground.
GVDD_AB	1	P	Gate-drive voltage supply; AB-side. Place 100 nF decoupling capacitor to GND.
GVDD_CD	22	P	Gate-drive voltage supply; CD-side. Place 100 nF decoupling capacitor to GND.
INPUT_A	5	I	PWM Input signal for half-bridge A. If unused, connect INPUT_A to GND.
INPUT_B	6	I	PWM Input signal for half-bridge B. If unused, connect INPUT_B to GND.
INPUT_C	14	I	PWM Input signal for half-bridge C. If unused, connect INPUT_C to GND.
INPUT_D	15	I	PWM Input signal for half-bridge D. If unused, connect INPUT_D to GND.
M1	19	I	Mode selection 1.
M2	20	I	Mode selection 2.
M3	21	I	Mode selection 3.
OC_ADJ	3	O	Over-Current threshold programming pin. Connect programming resistor to GND. Use 27 kΩ for typical applications.
OTW	17	O	Over-temperature warning; open drain; active low. Connect 10 kΩ pull-up resistor to DVDD to monitor. If unused, do not connect.
OUT_A	39, 40	O	Output, half-bridge A. If unused, remove BST_A capacitor and GND INPUT_A pin. Output pins can be left floating.
OUT_B	35	O	Output, half-bridge B. If unused, remove BST_B capacitor and GND INPUT_B pin. Output pins can be left floating.
OUT_C	32	O	Output, half-bridge C. If unused, remove BST_C capacitor and GND INPUT_C pin. Output pins can be left floating.
OUT_D	27, 28	O	Output, half-bridge D. If unused, remove BST_D capacitor and GND INPUT_D pin. Output pins can be left floating.
PVDD_AB	36, 37, 38	P	PVDD supply for half-bridge A and B. Place a minimum of 1 μF decoupling capacitor near PVDD_AB pin.
PVDD_CD	29, 30, 31	P	PVDD supply for half-bridge C and D. Place a minimum of 1 μF decoupling capacitor near PVDD_CD pin.
RESET	4	I	Device reset pin; active low.
VDD	2	P	12V power supply input for internal analog and digital voltage regulators.
PowerPAD™		P	Ground, connect to grounded heat sink.

(1) I = Input, O = Output, P = Power

Table 1. Mode Selection Pins

MODE PINS			PWM Input⁽¹⁾	Output Configuration	Input A	Input B	Input C	Input D	DC Speaker Protection⁽²⁾	Mode	C_START Capacitor
M3	M2	M1	PWM Input⁽¹⁾	Output Configuration	Input A	Input B	Input C	Input D	DC Speaker Protection⁽²⁾	Mode	C_START Capacitor
0	0	0	2N	2 x BTL	PWMa	PWMb	PWMc	PWMd	Enabled	AD	330 nF
0	0	1	1N⁽³⁾	2 x BTL	PWMa	Unused	PWMc	Unused	Enabled	AD	330 nF
0	1	0	2N	2 x BTL	PWMa	PWMb	PWMc	PWMd	Disabled	AD or BD	330 nF
0	1	1	2N/1N⁽³⁾	1 x BTL + 2 x SE⁽⁴⁾	PWMa	PWMb	PWMc	PWMd	Enabled (BTL only)	AD	1 μF
1	0	0	2N	1 x PBTL	PWMa	PWMb	0	0	Enabled	AD	330 nF
1	0	0	1N⁽³⁾	1 x PBTL	PWMa	Unused	0	1	Enabled	AD	330 nF
1	0	0	2N	1 x PBTL	PWMa	PWMb	1	0	Disabled	AD or BD	330 nF
1	0	1	1N1	4 x SE⁽⁵⁾	PWMa	PWMb	PWMc	PWMd	Disabled	AD	1 μF

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.

(2) DC Speaker Protection is disabled in BD mode due to in phase inductor ripple current.

(3) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.

(4) In [011] 1 x BTL + 2 x SE mode, Output A and B refers to the BTL channel, and Output C and D the SE channels

(5) The 4xSE mode can be used as 1 x BTL + 2 x SE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD