ZHCSPI8D November 2021 – July 2022 TLC6984
PRODUCTION DATA
After power on, the TLC6984 internal flag BANK_SEL, and counters LINE_COUNT, CHANNEL_COUNT, are all initialized to 0. Thus, the memory unit of channel R0/G0/B0, locating in line 0 of BANK A, is selected to restore the data transimitted the first time after VSYNC command.
When the first WRTGS command is received, all the data in the common shift register is latched into the memory unit of channel R0/G0/B0, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and LINE_COUNT stays the same. Thus, the memory unit of channel R1/G1/B1, locating in line 0 of BANK A, is selected to restore the data transimitted the second time after VSYNC command.
When the second WRTGS command is received, all the data in the common shift register is latched into the memory unit of channel R1/G1/B1, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and LINE_COUNT stays the same. Thus, the memory unit of channel R2/G2/B2, locating in line 0 of BANK A, is selected to restore the data transimitted the third time after VSYNC command.
Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then CHANNEL_COUNT is reset to 0 and LINE_COUNT increases by 1. Thus, the memory unit of channel R0/G0/B0, locating in line 1 of BANK A, is selected to restore the data transimitted the 17th time after VSYNC command.
Repeat this operation for each line until the LINE_COUNT exceeds the number of scan lines set in the SCAN_NUM (See FC0 register bit21-16 ) and all scan lines have been updated with new GS data, which means one frame of GS data is restored into the memory BANK. Then the LINE_COUNT is reset to 0.