ZHCSL89B may 2020 – november 2020 TPS3703
PRODUCTION DATA
The TPS3703 reset time delay is based on internal current source (ICT) to charge external capacitor (CCT) and read capacitor voltage with internal comparator. The minium value capacitor is 250 pF. There is no limitation on maximum capacitor the only constrain is imposed by the initial voltage of the capacitor, if CT cap is zero or near to zero then ideally there is no other constraint on the max capacitor. The typical ideal capacitor value needed for a given delay time can be calculated using Equation 1, where CCT is in nanofarads (nF) and tD is in ms:
To calculate the minimum and maximum-reset delay time use Equation 2 and Equation 3, respectively.
The slope of the equation is determined by the time the CT charging current (ICT) takes to charge the external capacitor up to the CT comparator threshold voltage (VCT). When RESET is asserted, the capacitor is discharged through the internal CT pulldown resistor. When the RESET conditions are cleared, the internal precision current source is enabled and begins to charge the external capacitor; when VCT = 1.15 V, RESET is unasserted. Note that in order to minimize the difference between the calculated RESET delay time and the actual RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize parasitic board capacitance around this pin. Table 9-2 lists the reset delay time ideal capacitor values for CCT.
| CCT | RESET DELAY TIME (tD), TYPICAL |
|---|---|
| 250 pF | 1.27 ms |
| 1 nF | 3.57 ms |
| 3.26 nF | 10.5 ms |
| 32.6 nF | 100.45 ms |
| 65.2 nF | 200.40 ms |
| 1uF | 3066.50 ms |