9.2.1.2.1 Output Voltage Setting

The output voltage can be calculated to:

Equation 5.

To minimize the current through the feedback divider network, R₂ should be within the range of 82 kΩ to 360 kΩ. The sum of R₁ and R₂ should not exceed approximately 1 MΩ, to keep the network robust against noise. An external feedforward capacitor C_ff is required for optimum regulation performance. R₁ and C_ff places a zero in the feedback loop.

Equation 6.

The value for C_ff can be calculated as:

Equation 7.

Table 1 shows a selection of suggested values for the feedback divider network for most common output voltages.

9.2.1.2.2 Output Filter Design (Inductor and Output Capacitor)

The TPS6212x operates with effective inductance values in the range of 10 µH to 33 µH and with effective output capacitance in the range of 1 µF to 33 µF. The device is optimized to operate for an output filter of L = 22 µH and C_OUT = 4.7 µF. Larger or smaller inductor and capacitor values can be used to optimize the performance of the device for specific operation conditions. For more details, see Checking Loop Stability.

9.2.1.2.3 Inductor Selection

The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple, and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The inductor ripple current (ΔI_L) decreases with higher inductance and increases with higher V_IN or V_OUT and can be estimated according to Equation 8.

Equation 9 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 9. This is recommended because during heavy load transient the inductor current will rise above the calculated value. A more conservative way is to select the inductor saturation current according to the high-side MOSFET switch current limit I_LIMF.

Equation 8.

Equation 9.

where

• T_ON = See Equation 1
• L = Inductor value
• ΔI_L = Peak-to-peak inductor ripple current
• I_Lmax = Maximum inductor current

In DC-DC converter applications, the efficiency is essentially affected by the inductor AC resistance (that is, quality factor) and by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current.

The total losses of the coil consist of both the losses in the DC resistance (R_(DC)) and the following frequency-dependent components:

• the losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• additional losses in the conductor from the skin effect (current displacement at high frequencies)
• magnetic field losses of the neighboring windings (proximity effect)
• radiation losses

The following inductor series from different suppliers have been used with the TPS6212x converters.

9.2.1.2.4 Output Capacitor Selection

The unique hysteretic PFM/PWM control scheme of the TPS6212x allows the use of ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents the converter operates in power save mode and the output voltage ripple is dependent on the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the voltage ripple in PFM mode and tighten DC output accuracy in PFM mode.

9.2.1.2.5 Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications a 4.7 µF to 10 µF ceramic capacitor is recommended. The voltage rating and DC bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased without any limit for better input voltage filtering.

For specific applications like energy harvesting a tantalum or tantalum polymer capacitor can be used to achieve a specific DC-DC converter input capacitance. Tantalum capacitors provide much better DC bias performance compared to ceramic capacitors. In this case a 1-µF or 2.2-µF ceramic capacitor should be used in parallel to provide low ESR.

Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or V_IN step on the input can induce large ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings.

Table 3 shows a list of input and output capacitors.

9.2.1.2.6 Checking Loop Stability

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

• Switching node, SW
• Inductor current, I_L
• Output ripple voltage, V_O(AC)

These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop, the load transient response is tested. During application of the load transient and the turn on of the high-side MOSFET switch, the output capacitor must supply all of the current required by the load. V_OUT immediately shifts by an amount equal to ΔI_(LOAD) × ESR, where ESR is the effective series resistance of C_OUT. ΔI_(LOAD) begins to charge or discharge C_OUT generating a feedback error signal used by the regulator to return V_OUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode.

During this recovery time, V_OUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET R_DS(on)) which are temperature dependent, the loop stability analysis should be done over the input voltage range, load current range, and temperature range