SPRUIM6A October 2018 – November 2020
The PCIe reference clock can be sourced by the SoC, clock generator, or PCIe card depending on whether the SoC is configured for Root complex (RC) or End point (EP). A programmable clock generator is used to generate the 100-MHz HCSL clock to drive the PCIe reference clock input of the SOC.
Resistor options are provided to select the clock source for PCIe RC and EP operation, as explained below.
For PCIe RC operation, the reference clock can be sourced directly from the SOC to the PCIe EP or from the clock generator to the SoC and PCIe EP. Selection can be made through jumpers, as shown in Table 5-1.
| Clock selected | Mount | Unmount |
|---|---|---|
| Reference clock for SOC from clock generator | R241 | R246 |
| R240 | R245 | |
| Reference clock for PCIe connector from SOC | R305 | R252 |
| R306 | R251 | |
| Reference clock for PCIe connector from clock generator | R252 | R305 |
| R251 | R306 |
For PCIe EP, the SOC clock input can be sourced by the PCIe RC or from the clock generator. Selection can be made through jumpers, as shown in Table 5-2.
| Clock selected | Mount | Unmount |
|---|---|---|
| Reference clock for SOC from clock generator | R241 | R246 |
| R240 | R245 | |
| Reference clock for SOC from PCIe connector | R246 | R241 |
| R245 | R240 |