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SNAS500Q May 2010 – May 2017 ADC12D1800

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

NXA|292
- MPBGAB2

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

4 Specifications

4.1 Absolute Maximum Ratings

(see ⁽¹⁾⁽²⁾)

	MIN	MAX	UNIT
Supply voltage (V_A, V_TC, V_DR, V_E)		2.2	V
Supply difference max(V_A/TC/DR/E) − min(V_A/TC/DR/E)	0	100	mV
Voltage on any input pin (except V_IN±)	−0.15	(V_A + 0.15)	V
V_IN± voltage range	–0.5	2.5	V
Ground difference max(GND_TC/DR/E) -min(GND_TC/DR/E)	0	100	mV
Input current at any pin⁽³⁾	–50	50	mA
ADC12D1800 package power dissipation at T_A ≤ 65°C⁽³⁾		4.95	W
Storage temperature, T_stg	–65	150	°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the Absolute Maximum Ratings. Section 4.3 indicates conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = GND_TC = GND_DR = GND_E = 0V, unless otherwise specified.

(3) When the input voltage at any pin exceeds the power supply limits (for example, less than GND or greater than V_A), the current at that pin should be limited to 50 mA. In addition, over-voltage at a pin must adhere to the maximum voltage limits. Simultaneous over-voltage at multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case.

4.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
		Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		Machine model (MM)	±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

(see ⁽¹⁾⁽²⁾)

		MIN	MAX	UNIT
Ambient temperature range	T_A ADC12D1800 (Standard JEDEC thermal model)	−40	50	°C
Ambient temperature range	T_A ADC12D1800 (Enhanced thermal model/heatsink)	−40	85	°C
T_J Junction temperature range (applies only to maximum operating speed)		120		°C
Supply voltage (V_A, V_TC, V_E)		+1.8	+2.0	V
Driver supply voltage (V_DR)		+1.8	V_A	V
V_IN+/- Voltage range⁽³⁾		–0.4	2.4 (DC-coupled)	V
V_IN+/- Differential voltage range⁽⁴⁾		1.0 (DC-coupled at 100% duty cycle) 2.0 (DC-coupled at 20% duty cycle) 2.8 (DC-coupled at 10% duty cycle)		V
V_IN+/- Current range⁽³⁾		–50	±50 peak (A.C.-coupled)	mA
V_IN+/- Power	(maintaining common mode voltage, A.C.-coupled)		15.3	dBm
V_IN+/- Power	(not maintaining common mode voltage, A.C.-coupled)		17.1	dBm
Ground difference max(GND_TC/DR/E) – min(GND_TC/DR/E)			0	V
CLK+/- Voltage range		0	V_A	V
Differential CLK amplitude V_P–P		0.4	2	V
Common mode input voltage V_CMI		V_CMO - 150	V_CMO + 150	mV

(2) All voltages are measured with respect to GND = GND_TC = GND_DR = GND_E = 0V, unless otherwise specified.

(3) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(4) This rating is intended for DC-coupled applications; the voltages listed may be safely applied to V_IN+/- for the life-time duty-cycle of the part.

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC12D1800	UNIT
		NXA (BGA)
		292 PINS
R_θJA	Junction-to-ambient thermal resistance	16	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	2.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

4.5 Converter Electrical Characteristics: Static Converter Characteristics

Unless otherwise specified, the following apply after calibration for V_A = V_DR = V_TC = V_E = +1.9V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; C_L = 10 pF; Differential, AC coupled Sine Wave Sampling Clock, f_CLK = 1.8 GHz at 0.5 V_P-P with 50% duty cycle (as specified); V_BG = Floating; Extended Control Mode with Register 6h written to 1C00h; Rext = Rtrim = 3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. Max limits are T_A = T_MIN to T_MAX, T_J < 105°C, unless otherwise noted.⁽¹⁾ ⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
	Resolution with no missing codes	T_A = T_MIN to T_MAX, T_J < 105°C		12	bits
INL	Integral non-linearity (Best fit)	1 MHz DC-coupled over-ranged sine wave	±2.5		LSB
DNL	Differential non-linearity	1 MHz DC-coupled over-ranged sine wave	±0.4		LSB
V_OFF	Offset error		5		LSB
V_OFF_ADJ	Input offset adjustment range	Extended Control Mode	±45		mV
PFSE	Positive full-scale error	See ⁽⁴⁾		±25	mV
NFSE	Negative full-scale error	See ⁽⁴⁾		±25	mV
	Out-of-range output code ⁽⁵⁾	(V_IN+) − (V_IN−) > + full scale		4095
	Out-of-range output code ⁽⁵⁾	(V_IN+) − (V_IN−) < − full scale		0

(1) The analog inputs, labeled I/O, are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

ADC12D1800 30123204.gif

(2) To ensure accuracy, it is required that V_A, V_TC, V_E and V_DR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.

(3) Typical figures are at T_A = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).

(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4-1. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.

(5) This parameter is ensured by design and is not tested in production.

4.6 Converter Electrical Characteristics: Dynamic Converter Characteristics

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
FPBW	Full power bandwidth	Non-DES Mode			2.8		GHz
		DESI, DESQ Mode			1.25		GHz
		DESIQ Mode			1.75		GHz
	Gain flatness	Non-DES Mode	D.C. to Fs/2		0.5		dB
		Non-DES Mode	D.C. to Fs		1.2		dB
		DESI, DESQ Mode	D.C. to Fs/2		4.0		dB
		DESIQ Mode	D.C. to Fs/2		3.6		dB
CER	Code error rate				10^-18		Error/Sample
NPR	Noise power ratio	See ⁽¹⁾			48.5		dB
IMD3	3rd order intermodulation distortion	DESIQ Mode FIN1 = 1212.52MHz at -7dBFS FIN2 = 1217.52 MHz at -7dBFS			-61		dBFS
IMD3	3rd order intermodulation distortion				-54		dBc
	Noise floor density	50Ω single-ended termination, DES Mode			-153.5		dBm/Hz
		50Ω single-ended termination, DES Mode			-152.5		dBFS/Hz
		Wideband input, DES Mode⁽²⁾			-152.6		dBm/Hz
		Wideband input, DES Mode⁽²⁾			-151.6		dBFS/Hz
NON-DES MODE⁽³⁾⁽⁴⁾
ENOB	Effective Number of Bits	A_IN = 125 MHz at -0.5 dBFS			9.4		bits
		A_IN = 248 MHz at -0.5 dBFS		8.4	9.2		bits
		A_IN = 498 MHz at -0.5 dBFS		8.4	9.1		bits
		A_IN = 1147 MHz at -0.5 dBFS			8.5		bits
		A_IN = 1448 MHz at -0.5 dBFS			8.4		bits
SINAD	Signal-to-Noise Plus Distortion Ratio	A_IN = 125 MHz at -0.5 dBFS			58		dB
		A_IN = 248 MHz at -0.5 dBFS		52.1	57.3		dB
		A_IN = 498 MHz at -0.5 dBFS		52.1	56.3		dB
		A_IN = 1147 MHz at -0.5 dBFS			52.9		dB
		A_IN = 1448 MHz at -0.5 dBFS			52.5		dB
SNR	Signal-to-Noise Ratio	A_IN = 125 MHz at -0.5 dBFS			58.6		dB
		A_IN = 248 MHz at -0.5 dBFS		52.9	57.8		dB
		A_IN = 498 MHz at -0.5 dBFS		52.9	57.3		dB
		A_IN = 1147 MHz at -0.5 dBFS			53.9		dB
		A_IN = 1448 MHz at -0.5 dBFS			53.1		dB
THD	Total Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS			-68.5		dB
		A_IN = 248 MHz at -0.5 dBFS		-60	-66.6		dB
		A_IN = 498 MHz at -0.5 dBFS		-60	-63.2		dB
		A_IN = 1147 MHz at -0.5 dBFS			-59.5		dB
		A_IN = 1448 MHz at -0.5 dBFS			-61.1		dB
2nd Harm	Second Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS			73		dBc
		A_IN = 248 MHz at -0.5 dBFS			87		dBc
		A_IN = 498 MHz at -0.5 dBFS			70		dBc
		A_IN = 1147 MHz at -0.5 dBFS			62		dBc
		A_IN = 1448 MHz at -0.5 dBFS			66		dBc
3rd Harm	Third Harmonic Distortion	A_IN = 125 MHz at -0.5 dBFS			76.8		dBc
		A_IN = 248 MHz at -0.5 dBFS			67.4		dBc
		A_IN = 498 MHz at -0.5 dBFS			66.3		dBc
		A_IN = 1147 MHz at -0.5 dBFS			63		dBc
		A_IN = 1448 MHz at -0.5 dBFS			63.6		dBc
SFDR	Spurious-Free Dynamic Range	A_IN = 125 MHz at -0.5 dBFS			73		dBc
		A_IN = 248 MHz at -0.5 dBFS			67.5	58	dBc
		A_IN = 498 MHz at -0.5 dBFS			66.1	58	dBc
		A_IN = 1147 MHz at -0.5 dBFS			60.2		dBc
		A_IN = 1448 MHz at -0.5 dBFS			60.3		dBc
DES MODE⁽³⁾⁽⁴⁾ ⁽⁵⁾
ENOB	Effective number of bits	A_IN = 125 MHz at -0.5 dBFS			8.9		bits
		A_IN = 248 MHz at -0.5 dBFS			8.8	8.4	bits
		A_IN = 498 MHz at -0.5 dBFS			8.6		bits
		A_IN = 1147 MHz at -0.5 dBFS			8		bits
		A_IN = 1448 MHz at -0.5 dBFS			8		bits
SINAD	Signal-to-noise plus distortion ratio	A_IN = 125 MHz at -0.5 dBFS			55.6		dB
		A_IN = 248 MHz at -0.5 dBFS			54.8	52.1	dB
		A_IN = 498 MHz at -0.5 dBFS			53.8		dB
		A_IN = 1147 MHz at -0.5 dBFS			50		dB
		A_IN = 1448 MHz at -0.5 dBFS			49.8		dB
SNR	Signal-to-noise ratio	A_IN = 125 MHz at -0.5 dBFS			55.8		dB
		A_IN = 248 MHz at -0.5 dBFS			55.3	52.9	dB
		A_IN = 498 MHz at -0.5 dBFS			54.5		dB
		A_IN = 1147 MHz at -0.5 dBFS			50.4		dB
		A_IN = 1448 MHz at -0.5 dBFS			50.1		dB
THD	Total harmonic distortion	A_IN = 125 MHz at -0.5 dBFS			-67.8		dB
		A_IN = 248 MHz at -0.5 dBFS			-65	-60	dB
		A_IN = 498 MHz at -0.5 dBFS			-62		dB
		A_IN = 1147 MHz at -0.5 dBFS			-60.6		dB
		A_IN = 1448 MHz at -0.5 dBFS			-61.9		dB
2nd Harm	Second harmonic distortion	A_IN = 125 MHz at -0.5 dBFS			78		dBc
		A_IN = 248 MHz at -0.5 dBFS			74.4		dBc
		A_IN = 498 MHz at -0.5 dBFS			72.5		dBc
		A_IN = 1147 MHz at -0.5 dBFS			70.5		dBc
		A_IN = 1448 MHz at -0.5 dBFS			72.8		dBc
3rd Harm	Third harmonic distortion	A_IN = 125 MHz at -0.5 dBFS			72.6		dBc
		A_IN = 248 MHz at -0.5 dBFS			66.5		dBc
		A_IN = 498 MHz at -0.5 dBFS			63.2		dBc
		A_IN = 1147 MHz at -0.5 dBFS			61.8		dBc
		A_IN = 1448 MHz at -0.5 dBFS			63.8		dBc
SFDR	Spurious-free dynamic range	A_IN = 125 MHz at -0.5 dBFS			58.9		dBc
		A_IN = 248 MHz at -0.5 dBFS			60.4	58	dBc
		A_IN = 498 MHz at -0.5 dBFS			60.5		dBc
		A_IN = 1147 MHz at -0.5 dBFS			56.7		dBc
		A_IN = 1448 MHz at -0.5 dBFS			55.6		dBc

(1) The NPR was measured using an Agilent N6030A Arbitrary Waveform Generator (ARB) to generate the input signal. See the Wideband Performance for an example spectrum. The "noise" portion of the signal was created by tones spaced at 500 kHz and the "notch" was a 25 MHz absence of tones centered at 320 MHz. The bandwidth of this equipment is only 500 MHz, so the final reported NPR was extrapolated from the measured NPR as if the entire Nyquist band were occupied with noise.

(2) The Noise Floor Density was measured for two conditions: the analog input terminated with 50Ω, and in the presence of a 500 MHz wideband noise signal with total power just below the maximum input level to the ADC. In both cases, the spurs at DC, Fs/4 and Fs/2 were not included in the noise floor calculation. The power over the entire Nyquist band (except for the noise signal) was integrated and the average number is reported.

(3) The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic performance vs. temperature in the Typical Performance Plots to see typical performance from cold to room temperature (-40°C to 25°C).

(4) The Fs/2 spur was removed from all the dynamic performance specifications.

(5) These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature is used to reduce the interleaving timing spur amplitude, which occurs at fs/2-fin, and thereby increase the SFDR, SINAD and ENOB.

4.7 Converter Electrical Characteristics: Analog Input and Output and Reference Characteristics

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_{IN_FSR}	Analog differential input full scale range	Non-Extended Control Mode	FSR Pin High	740	800	860	mV_P-P
		Extended Control Mode	FM(14:0) = 4000h (default)		800		mV_P-P
		Extended Control Mode	FM(14:0) = 7FFFh		1000		mV_P-P
C_IN	Analog input capacitance, non-DES mode ⁽¹⁾ ⁽²⁾	Differential			0.02		pF
	Analog input capacitance, non-DES mode ⁽¹⁾ ⁽²⁾	Each input pin to ground			1.6		pF
	Analog input capacitance, DES mode ⁽¹⁾ ⁽²⁾	Differential			0.08		pF
	Analog input capacitance, DES mode ⁽¹⁾ ⁽²⁾	Each input pin to ground			2.2		pF
R_IN	Differential input resistance			91	100	109	Ω
COMMON MODE OUTPUT
V_CMO	Common mode output voltage	I_CMO = ±100 µA		1.15	1.25	1.35	V
TC_V_CMO	Common mode output voltage temperature coefficient	I_CMO = ±100 µA			38		ppm/°C
V_{CMO_LVL}	V_CMO input threshold to set DC-coupling Mode				0.63		V
C_L_V_CMO	Maximum V_CMO load capacitance	⁽¹⁾				80	pF
BANDGAP REFERENCE
V_BG	Bandgap reference output voltage	I_BG = ±100 µA		1.15	1.25	1.35	V
TC_V_BG	Bandgap reference voltage temperature coefficient	I_BG = ±100 µA			32		ppm/°C
C_L_V_BG	Maximum bandgap reference load capacitance	⁽¹⁾				80	pF

(1) This parameter is ensured by design and is not tested in production.

(2) The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown below.

ADC12D1800 30123295.gif

4.8 Converter Electrical Characteristics: I-Channel to Q-Channel Characteristics

PARAMETER		TEST CONDITIONS	TYP	UNIT
	Offset match		2	LSB
	Positive full-scale match	Zero offset selected in Control Register	2	LSB
	Negative full-scale match	Zero offset selected in Control Register	2	LSB
	Phase matching (I, Q)	f_IN = 1.0 GHz	< 1	Degree
X-TALK	Crosstalk from I-channel (Aggressor) to Q-channel (Victim)	Aggressor = 867 MHz F.S. Victim = 100 MHz F.S.	−70	dB
X-TALK	Crosstalk from Q-channel (Aggressor) to I-channel (Victim)	Aggressor = 867 MHz F.S. Victim = 100 MHz F.S.	−70	dB

4.9 Converter Electrical Characteristics: Sampling Clock Characteristics

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{IN_CLK}	Differential sampling clock input level ⁽¹⁾	Sine wave clock Differential Peak-to-peak	0.4	0.6	2.0	V_P-P
V_{IN_CLK}	Differential sampling clock input level ⁽¹⁾	Square wave clock Differential peak-to-peak	0.4	0.6	2.0	V_P-P
C_{IN_CLK}	Sampling clock input capacitance ⁽²⁾	Differential		0.1		pF
C_{IN_CLK}	Sampling clock input capacitance ⁽²⁾	Each input to ground		1		pF
R_{IN_CLK}	Sampling clock differential input resistance			100		Ω

(1) This parameter is ensured by design and/or characterization and is not tested in production.

(2) This parameter is ensured by design and is not tested in production.

4.10 Converter Electrical Characteristics: AutoSync Feature Characteristics

PARAMETER		TEST CONDITIONS	TYP	UNIT
V_{IN_RCLK}	Differential RCLK input level	Differential peak-to-peak	360	mV_P-P
C_{IN_RCLK}	RCLK input capacitance	Differential	0.1	pF
C_{IN_RCLK}	RCLK input capacitance	Each input to ground	1	pF
R_{IN_RCLK}	RCLK differential input resistance		100	Ω
I_{IH_RCLK}	Input leakage current; V_IN = V_A		22	µA
I_{IL_RCLK}	Input leakage current; V_IN = GND		-33	µA
V_{O_RCOUT}	Differential RCOut Output Voltage		360	mV

4.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
V_IH	Logic high input voltage		0.7×V_A		0.3×V_A	V
V_IL	Logic low input voltage		0.7×V_A		0.3×V_A	V
I_IH	Input leakage current; V_IN = V_A			0.02		μA
I_IL	Input leakage current; V_IN = GND	FSR, CalDly, CAL, NDM, TPM, DDRPh, DES		-0.02		μA
		SCS, SCLK, SDI		-17		μA
		PDI, PDQ, ECE		-38		μA
C_{IN_DIG}	Digital control pin input capacitance ⁽¹⁾	Measured from each control pin to GND		1.5		pF
DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ)
V_OD	LVDS differential output voltage	V_BG = Floating, OVS = High	400	630	800	mV_P-P
		V_BG = Floating, OVS = Low	230	460	630	mV_P-P
		V_BG = V_A, OVS = High		670		mV_P-P
		V_BG = V_A, OVS = Low		500		mV_P-P
ΔV_{O DIFF}	Change in LVDS output swing between logic levels			±1		mV
V_OS	Output offset voltage	V_BG = Floating		0.8		V
V_OS	Output offset voltage	V_BG = V_A		1.2		V
ΔV_OS	Output offset voltage change between logic levels			±1		mV
I_OS	Output short circuit current	V_BG = Floating; D+ and D− connected to 0.8V		±4		mA
Z_O	Differential output impedance			100		Ω
V_OH	Logic high output level	CalRun, I_OH = −100 µA, ⁽²⁾ SDO, I_OH = −400 µA ⁽²⁾		1.65		V
V_OL	Logic low output level	CalRun, I_OL = 100 µA, ⁽²⁾ SDO, I_OL = 400 µA ⁽²⁾		0.15		V
DIFFERENTIAL DCLK RESET PINS (DCLK_RST)
V_{CMI_DRST}	DCLK_RST common mode input voltage			1.25		V
V_{ID_DRST}	Differential DCLK_RST input voltage			V_{IN_CLK}		V_P-P
R_{IN_DRST}	Differential DCLK_RST input resistance	⁽¹⁾		100		Ω

(1) This parameter is ensured by design and is not tested in production.

(2) This parameter is ensured by design and/or characterization and is not tested in production.

4.12 Converter Electrical Characteristics: Power Supply Characteristics

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
I_A	Analog supply current	PDI = PDQ = Low		1345		mA
		PDI = Low; PDQ = High		730		mA
		PDI = High; PDQ = Low		730		mA
		PDI = PDQ = High		15		mA
I_TC	Track-and-hold and clock supply current	PDI = PDQ = Low		495		mA
		PDI = Low; PDQ = High		295		mA
		PDI = High; PDQ = Low		295		mA
		PDI = PDQ = High		4		mA
I_DR	Output driver supply current	PDI = PDQ = Low		330		mA
		PDI = Low; PDQ = High		175		mA
		PDI = High; PDQ = Low		175		mA
		PDI = PDQ = High		3		mA
I_E	Digital encoder supply current	PDI = PDQ = Low		165		mA
		PDI = Low; PDQ = High		85		mA
		PDI = High; PDQ = Low		85		mA
		PDI = PDQ = High		1		mA
I_TOTAL	Total supply current	1:2 Demux Mode PDI = PDQ = Low		2335	2481	mA
I_TOTAL	Total supply current	Non-Demux Mode PDI = PDQ = Low		2200		mA
P_C	Power consumption	1:2 Demux Mode	PDI = PDQ = Low	4.44	4.7	W
			PDI = Low; PDQ = High	2.44		W
			PDI = High; PDQ = Low	2.44		W
			PDI = PDQ = High	43.7		mW
		Non-Demux Mode	PDI = PDQ = Low	4.18		W

4.13 Converter Electrical Characteristics: AC Electrical Characteristics

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SAMPLING CLOCK (CLK)
f_{CLK (max)}	Maximum sampling clock frequency				1.8	GHz
f_{CLK (min)}	Minimum sampling clock frequency	Non-DES Mode; LFS = 0b			300	MHz
		Non-DES Mode; LFS = 1b			150	MHz
		DES Mode			500	MHz
	Sampling clock duty cycle	f_CLK(min) ≤ f_CLK ≤ f_CLK(max)⁽¹⁾	20%	50%	80%
t_CL	Sampling clock low time	See ⁽²⁾	111	278		ps
t_CH	Sampling clock high time	See ⁽²⁾	111	278		ps
DATA CLOCK (DCLKI, DCLKQ)
	DCLK duty cycle	See ⁽²⁾	45%	50%	55%
t_SR	Setup time DCLK_RST±	See ⁽¹⁾		45		ps
t_HR	Hold time DCLK_RST±	See ⁽¹⁾		45		ps
t_PWR	Pulse width DCLK_RST±	See ⁽²⁾	5			Sampling clock cycles
t_{SYNC_DLY}	DCLK synchronization delay	90° Mode⁽²⁾			4	Sampling clock cycles
t_{SYNC_DLY}	DCLK synchronization delay	0° Mode⁽²⁾			5	Sampling clock cycles
t_LHT	Differential low-to-high transition time	10%-to-90%, C_L = 2.5 pF		200		ps
t_HLT	Differential high-to-low transition time	10%-to-90%, C_L = 2.5 pF		200		ps
t_SU	Data-to-DCLK setup time	90° Mode⁽²⁾		430		ps
t_H	DCLK-to-data hold time	90° Mode⁽²⁾		430		ps
t_OSK	DCLK-to-data output skew	50% of DCLK transition to 50% of Data transition⁽²⁾		±50		ps
DATA INPUT-TO-OUTPUT
t_AD	Aperture delay	Sampling CLK+ rise to acquisition of data		1.15		ns
t_AJ	Aperture jitter			0.2		ps (rms)
t_OD	Sampling clock-to data output delay (in addition to latency)	50% of sampling clock transition to 50% of data transition		3.2		ns
t_LAT	Latency in 1:2 Demux non-DES mode⁽²⁾	DI, DQ outputs			34	Sampling clock cycles
	Latency in 1:2 Demux non-DES mode⁽²⁾	DId, DQd outputs			35
	Latency in 1:4 Demux DES mode⁽²⁾	DI outputs			34
		DQ outputs			34.5
		DId outputs			35
		DQd outputs			35.5
	Latency in non-Demux non-DES mode⁽²⁾	DI outputs			34
	Latency in non-Demux non-DES mode⁽²⁾	DQ outputs			34
	Latency in non-Demux DES mode⁽²⁾	DI outputs			34
	Latency in non-Demux DES mode⁽²⁾	DQ Outputs			34.5
t_ORR	Over range recovery time	Differential V_IN step from ±1.2V to 0V to accurate conversion		1		Sampling clock cycle
t_WU	Wake-up time (PDI/PDQ low to rated accuracy conversion)	Non-DES Mode⁽²⁾		500		ns
t_WU	Wake-up time (PDI/PDQ low to rated accuracy conversion)	DES Mode⁽²⁾		1		µs

(1) This parameter is ensured by design and/or characterization and is not tested in production.

(2) This parameter is ensured by design and is not tested in production.

4.14 Converter Timing Requirements: Serial Port Interface

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

		MIN	NOM	UNIT
f_SCLK	Serial clock frequency ⁽¹⁾		15	MHz
	Serial clock low time	30		ns
	Serial clock high time	30		ns
t_SSU	Serial data-to-serial clock rising setup time ⁽¹⁾		2.5	ns
t_SH	Serial data-to-serial clock rising hold time ⁽¹⁾		1	ns
t_SCS	SCS-to-serial clock rising setup time		2.5	ns
t_HCS	SCS-to-serial clock falling hold time		1.5	ns
t_BSU	Bus turn-around time		10	ns

(1) This parameter is ensured by design and is not tested in production.

4.15 Converter Switching Characteristics: Calibration

Limits are T_A = T_MIN to T_MAX, T_J < 105°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_CAL	Calibration cycle time	Non-ECM		5.2·10⁷		Sampling clock cycles
		ECM CSS = 0b
		ECM CSS = 1b
t_{CAL_L}	CAL pin low time	See ⁽¹⁾	1280			Sampling clock cycles
t_{CAL_H}	CAL pin high time	See ⁽¹⁾	1280			Sampling clock cycles
t_CalDly	Calibration delay determined by CalDly pin⁽¹⁾	CalDly = low			2²⁴	Sampling clock cycles
t_CalDly	Calibration delay determined by CalDly pin⁽¹⁾	CalDly = high			2³⁰	Sampling clock cycles

(1) This parameter is ensured by design and is not tested in production.

Figure 4-1 Input / Output Transfer Characteristic

The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 4-2 Clocking in 1:2 Demux Non-DES Mode

Figure 4-3 Clocking in Non-Demux Non-DES Mode

Figure 4-4 Clocking in 1:4 Demux DES Mode

Figure 4-5 Clocking in Non-Demux Mode DES Mode

Figure 4-6 Data Clock Reset Timing (Demux Mode)

Figure 4-7 Power-on and On-Command Calibration Timing

Figure 4-8 Serial Interface Timing

4.16 Typical Characteristics

V_A= V_DR = V_TC = V_E = 1.9V, f_CLK = 1.8 GHz, f_IN = 498 MHz, T_A= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25 MHz, fc = 320 MHz.