ZHCSBL4A September 2013 – January 2015
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 說(shuō)明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Device Power Up
- 8.3.2 Power Path Management
- 8.3.3 Battery Charging Management
- 8.3.4 Status Outputs (STAT, and INT)
- 8.3.5 Protections
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Map
- 8.6.1
I2C Registers
- 8.6.1.1 Input Source Control Register REG00 [reset = 01011000, or 58]
- 8.6.1.2 Power-On Configuration Register REG01 [reset = 00011011, or 0x1B]
- 8.6.1.3 Charge Current Control Register REG02 [reset = 00100000, or 0x20]
- 8.6.1.4 Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]
- 8.6.1.5 Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]
- 8.6.1.6 Charge Termination/Timer Control Register REG05 [reset = 10011100, or 0x9C]
- 8.6.1.7 Boost Voltage/Thermal Regulation Control Register REG06 [reset = 10010011, or 0x93]
- 8.6.1.8 Misc Operation Control Register REG07 [reset = 01001011, or 4B]
- 8.6.1.9 System Status Register REG08
- 8.6.1.10 New Fault Register REG09
- 8.6.1.11 Vender / Part / Revision Status Register REG0A
- 8.6.1
I2C Registers
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購(gòu)信息
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 51) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.
- Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.
- Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
- Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane.
- Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using thermal pad as the single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground.
- Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
- Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
- It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
- The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the VQFN information, refer to SCBA017 and SLUA271.
Figure 51. High Frequency Current Path
11.2 Layout Example
Figure 52. Layout Example