ZHCSFS1A December 2016 – June 2018 SN65DSI84-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1
Control and Status Registers Overview
- 8.6.1.1 CSR Bit Field Definitions – ID Registers
- 8.6.1.2 CSR Bit Field Definitions – Reset and Clock Registers
- 8.6.1.3 CSR Bit Field Definitions – DSI Registers
- 8.6.1.4 CSR Bit Field Definitions – LVDS Registers
- 8.6.1.5
CSR Bit Field Definitions – Video Registers
- 8.6.1.5.1 Register 0x20
- 8.6.1.5.2 Register 0x21
- 8.6.1.5.3 Register 0x24
- 8.6.1.5.4 Register 0x25
- 8.6.1.5.5 Register 0x28
- 8.6.1.5.6 Register 0x29
- 8.6.1.5.7 Register 0x2C
- 8.6.1.5.8 Register 0x2D
- 8.6.1.5.9 Register 0x30
- 8.6.1.5.10 Register 0x31
- 8.6.1.5.11 Register 0x34
- 8.6.1.5.12 Register 0x36
- 8.6.1.5.13 Register 0x38
- 8.6.1.5.14 Register 0x3A
- 8.6.1.5.15 Register 0x3C
- 8.6.1.6 CSR Bit Field Definitions – IRQ Registers
- 8.6.1
Control and Status Registers Overview
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PAP|64
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- PAP|64
訂購信息
8.4.4 DSI Lane Merging
The SN65DSI84-Q1 supports four DSI data lanes per input channel, and may be configured to support one, two, or three DSI data lanes per channel. Unused DSI input pins on the SN65DSI84-Q1 should be left unconnected or driven to LP11 state. The bytes received from the data lanes are merged in HS mode to form packets that carry the video stream. DSI data lanes are bit and byte aligned.
Figure 12 illustrates the lane merging function for each channel; 4-Lane, 3-Lane, and 2-Lane modes are illustrated
Figure 12. SN65DSI84-Q1 DSI Lane Merging Illustration