ZHCSFS1A December 2016 – June 2018 SN65DSI84-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1
Control and Status Registers Overview
- 8.6.1.1 CSR Bit Field Definitions – ID Registers
- 8.6.1.2 CSR Bit Field Definitions – Reset and Clock Registers
- 8.6.1.3 CSR Bit Field Definitions – DSI Registers
- 8.6.1.4 CSR Bit Field Definitions – LVDS Registers
- 8.6.1.5
CSR Bit Field Definitions – Video Registers
- 8.6.1.5.1 Register 0x20
- 8.6.1.5.2 Register 0x21
- 8.6.1.5.3 Register 0x24
- 8.6.1.5.4 Register 0x25
- 8.6.1.5.5 Register 0x28
- 8.6.1.5.6 Register 0x29
- 8.6.1.5.7 Register 0x2C
- 8.6.1.5.8 Register 0x2D
- 8.6.1.5.9 Register 0x30
- 8.6.1.5.10 Register 0x31
- 8.6.1.5.11 Register 0x34
- 8.6.1.5.12 Register 0x36
- 8.6.1.5.13 Register 0x38
- 8.6.1.5.14 Register 0x3A
- 8.6.1.5.15 Register 0x3C
- 8.6.1.6 CSR Bit Field Definitions – IRQ Registers
- 8.6.1
Control and Status Registers Overview
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PAP|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PAP|64
訂購信息
8.4.6 DSI Video Transmission Specifications
The SN65DSI84-Q1 supports burst video mode and non-burst video mode with sync events or with sync pulses packet transmission as described in the DSI specification. The burst mode supports time-compressed pixel stream packets that leave added time per scan line for power savings LP mode. The SN65DSI84-Q1 requires a transition to LP mode once per frame to enable PHY synchronization with the DSI host processor; however, for a robust and low-power implementation, the transition to LP mode is recommended on every video line.
Figure 16 illustrates the DSI video transmission applied to SN65DSI84-Q1 applications. In all applications, the LVDS output rate must be less than or equal to the DSI input rate. The first line of a video frame shall start with a VSS packet, and all other lines start with VSE or HSS. The position of the synchronization packets in time is of utmost importance because this has a direct impact on the visual performance of the display panel; that is, these packets generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface after the delay programmed into CHA_SYNC_DELAY_LOW/HIGH (CSR 0x28.7:0 and 0x29.3:0).
As required in the DSI specification, the SN65DSI84-Q1 requires that pixel stream packets contain an integer number of pixels (i.e. end on a pixel boundary); TI recommends transmitting an entire scan line on one pixel stream packet. When a scan line is broken in to multiple packets, inter-packet latency shall be considered such that the video pipeline (ie. pixel queue or partial line buffer) does not run empty (i.e. under-run); during scan line processing, if the pixel queue runs empty, the SN65DSI84-Q1 transmits zero data (18’b0 or 24’b0) on the LVDS interface.
NOTE
When the HS clock is used as a source for the LVDS pixel clock, the LP mode transitions apply only to the data lanes, and the DSI clock lane remains in the HS mode during the entire video transmission.
The DSI84 does not support the DSI Virtual Channel capability or reverse direction (peripheral to processor) transmissions.
Figure 16. DSI Channel Transmission and Transfer Function