SLVS774C June 2007 – January 2016 TPS650240 , TPS650241 , TPS650242 , TPS650243 , TPS650244 , TPS650245
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics: Control Signals and Supply Pins
- 7.6 Electrical Characteristics: VDCDC1 Step-Down Converter
- 7.7 Electrical Characteristics: VDCDC2 Step-Down Converter
- 7.8 Electrical Characteristics: VDCDC3 Step-Down Converter
- 7.9 Electrical Characteristics: General
- 7.10 Typical Characteristics
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購信息
11 Layout
11.1 Layout Guidelines
- The input capacitors for the DC-DC converters must be placed as close as possible to the VINDCDCx and VCC pins.
- The inductor of the output filter must be placed as close as possible to the device to provide the shortest switch node possible, reducing the noise emitted into the system and increasing the efficiency.
- Sense the feedback voltage of the output at the output capacitors to ensure the best DC accuracy. Feedback must be routed away from noisy sources such as the inductor. If possible route on the opposite side from the switch node and inductor and place a GND plane between the feedback and the noisy sources or a keep-out underneath them entirely.
- Place the output capacitors as close as possible to the inductor to reduce the feedback loop. This ensures the best regulation at the feedback point.
- Place the device as close as possible to the most demanding or sensitive load. The output capacitors must be placed close to the input of the load. This ensures the best AC performance possible.
- The input and output capacitors for the LDOs must be placed close to the device for best regulation performance.
- Use vias to connect thermal pad to ground plane.
- A common ground plane is recommended for the layout of this device. The AGND can be separated from the PGND, but a large low-parasitic PGND is required to connect the PGNDx pins to the CIN and external PGND connections. If the AGND and PGND planes are separated, have one connection point to reference the grounds together. Place this connection point close to the IC.
11.2 Layout Example
Figure 23. Layout Diagram