ZHCSLY5A August 2020 – July 2021 TPS65994AD
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Recommended Capacitance
- 6.5 Thermal Information
- 6.6 Power Supply Characteristics
- 6.7 Power Consumption
- 6.8 PP_5V Power Switch Characteristics
- 6.9 PP_EXT Power Switch Characteristics
- 6.10 Power Path Supervisory
- 6.11 CC Cable Detection Parameters
- 6.12 CC VCONN Parameters
- 6.13 CC PHY Parameters
- 6.14 Thermal Shutdown Characteristics
- 6.15 ADC Characteristics
- 6.16 Input/Output (I/O) Characteristics
- 6.17 I2C Requirements and Characteristics
- 6.18 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 USB-PD Physical Layer
- 8.3.2 Power Management
- 8.3.3
Power Paths
- 8.3.3.1
Internal Sourcing Power Paths
- 8.3.3.1.1 PP_5Vx Current Clamping
- 8.3.3.1.2 PP_5Vx Local Overtemperature Shut Down (OTSD)
- 8.3.3.1.3 PP_5Vx Current Sense
- 8.3.3.1.4 PP_5Vx OVP
- 8.3.3.1.5 PP_5Vx UVLO
- 8.3.3.1.6 PP_5Vx Reverse Current Protection
- 8.3.3.1.7 Fast Role Swap
- 8.3.3.1.8 PP_CABLE Current Clamp
- 8.3.3.1.9 PP_CABLE Local Overtemperature Shut Down (OTSD)
- 8.3.3.1.10 PP_CABLE UVLO
- 8.3.3.2 Sink Path Control
- 8.3.3.1
Internal Sourcing Power Paths
- 8.3.4 Cable Plug and Orientation Detection
- 8.3.5 Default Behavior Configuration (ADCIN1, ADCIN2)
- 8.3.6 ADC
- 8.3.7 DisplayPort Hot-Plug Detect (HPD)
- 8.3.8 Digital Interfaces
- 8.3.9 Digital Core
- 8.3.10 I2C Interface
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
訂購信息
8.3.2 Power Management
The TPS65994AD power management block receives power and generates voltages to provide power to the TPS65994AD internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 may also be used as a low power output for external EEPROM memory. The power supply path is shown in Figure 8-9.
Figure 8-9 Power SuppliesThe TPS65994AD is powered from either VIN_3V3, PA_VBUS, or PB_VBUS. The normal power supply input is VIN_3V3. When powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V circuitry and I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5-V core digital circuitry. When VIN_3V3 power is unavailable and power is available on PA_VBUS, or PB_VBUS it is referred to as the dead-battery startup condition. In a dead-battery startup condition, the TPS65994AD opens the VIN_3V3 switch until the host clears the dead-battery flag via I2C. Therefore, the TPS65994AD is powered from the VBUS input with the higher voltage during the dead-battery startup condition and until the dead-battery flag is cleared. When powering from a VBUS input, the voltage on PA_VBUS, or PB_VBUS is stepped down through an LDO to LDO_3V3.