ZHCSLY5A August 2020 – July 2021 TPS65994AD
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Recommended Capacitance
- 6.5 Thermal Information
- 6.6 Power Supply Characteristics
- 6.7 Power Consumption
- 6.8 PP_5V Power Switch Characteristics
- 6.9 PP_EXT Power Switch Characteristics
- 6.10 Power Path Supervisory
- 6.11 CC Cable Detection Parameters
- 6.12 CC VCONN Parameters
- 6.13 CC PHY Parameters
- 6.14 Thermal Shutdown Characteristics
- 6.15 ADC Characteristics
- 6.16 Input/Output (I/O) Characteristics
- 6.17 I2C Requirements and Characteristics
- 6.18 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 USB-PD Physical Layer
- 8.3.2 Power Management
- 8.3.3
Power Paths
- 8.3.3.1
Internal Sourcing Power Paths
- 8.3.3.1.1 PP_5Vx Current Clamping
- 8.3.3.1.2 PP_5Vx Local Overtemperature Shut Down (OTSD)
- 8.3.3.1.3 PP_5Vx Current Sense
- 8.3.3.1.4 PP_5Vx OVP
- 8.3.3.1.5 PP_5Vx UVLO
- 8.3.3.1.6 PP_5Vx Reverse Current Protection
- 8.3.3.1.7 Fast Role Swap
- 8.3.3.1.8 PP_CABLE Current Clamp
- 8.3.3.1.9 PP_CABLE Local Overtemperature Shut Down (OTSD)
- 8.3.3.1.10 PP_CABLE UVLO
- 8.3.3.2 Sink Path Control
- 8.3.3.1
Internal Sourcing Power Paths
- 8.3.4 Cable Plug and Orientation Detection
- 8.3.5 Default Behavior Configuration (ADCIN1, ADCIN2)
- 8.3.6 ADC
- 8.3.7 DisplayPort Hot-Plug Detect (HPD)
- 8.3.8 Digital Interfaces
- 8.3.9 Digital Core
- 8.3.10 I2C Interface
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
訂購信息
5 Pin Configuration and Functions
Figure 5-1 RSL Package48-pin QFNTop ViewTable 5-1 Pin Functions
| PIN | TYPE | RESET | Description | |
|---|---|---|---|---|
| NAME | NO. | |||
| ADCIN1 | 33 | I | Hi-Z | Configuration input. Connect to a resistor divider to LDO_3V3. |
| ADCIN2 | 35 | I | Hi-Z | Configuration input. Connect to a resistor divider to LDO_3V3. |
| GND | 36 | — | — | Ground. Connect to ground plane. |
| GPIO0 | 45 | I/O | Hi-Z | General purpose digital I/O. Tie to PP5V or ground when unused. May be used as DisplayPort HPD signal for Port B. |
| GPIO1 | 38 | I/O | Hi-Z | General purpose digital I/O. Tie to PP5V or ground when unused. May be used as DisplayPort HPD signal for Port A. |
| GPIO2 | 9 | I/O | Hi-Z | General purpose digital I/O. Tie to PP5V or ground when unused. |
| GPIO3 | 28 | I/O | Hi-Z | General purpose digital I/O. Tie to PP5V or ground when unused. |
| GPIO4 | 2 | I/O | Hi-Z | General purpose digital I/O. May be used as an ADC input. Tie to PP5V or ground when unused. |
| GPIO5 | 46 | I/O | Hi-Z | General purpose digital I/O. May be used as an ADC input. Tie to PP5V or ground when unused. |
| GPIO6 | 29 | I/O | Hi-Z | General purpose digital I/O. Tie to PP5V or ground when unused. |
| GPIO7 | 27 | I/O | Hi-Z | General purpose digital I/O. Tie to PP5V or ground when unused. |
| GPIO8 | 10 | I/O | Hi-Z | General purpose digital I/O. Tie to PP5V or ground when unused. |
| GPIO9 | 8 | O | Hi-Z | General purpose digital output. Tie to PP5V or ground when unused. |
| I2C_EC_SCL | 42 | I | Hi-Z | I2C slave serial clock input. Tie to pullup voltage through a resistor. May be grounded if unused. Connect to Embedded Controller (EC). |
| I2C_EC_SDA | 40 | I/O | Hi-Z | I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. Connect to Embedded Controller (EC). |
| I2C_EC_IRQ | 43 | O | Hi-Z | I2C slave interrupt. Active low. Connect to external voltage through a pull-up resistor. Connect to Embedded Controller (EC). This can be re-configured to GPIO10. May be grounded if unused. |
| I2C2s_SCL | 41 | I | Hi-Z | I2C slave serial clock input. Tie to pull-up voltage through a resistor. May be grounded if unused. |
| I2C2s_SDA | 44 | I/O | Hi-Z | I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a resistor. May be grounded if unused. |
| I2C2s_IRQ | 39 | O | Hi-Z | I2C slave interrupt. Active low. Connect to external voltage through a pull-up resistor. Tie to PP5V or ground when unused. This can be re-configured to GPIO11. |
| I2C3m_SCL | 1 | O | Hi-Z | I2C master serial clock. Open-drain output. Tie to pullup voltage through a resistor when used or unused. |
| I2C3m_SDA | 48 | I/O | Hi-Z | I2C master serial data. Open-drain input/output. Tie to pullup voltage through a resistor when used or unused. |
| I2C3m_IRQ | 47 | I | Hi-Z | I2C master interrupt. Active low. Connect to external voltage through a pull-up resistor. Tie to PP5V or ground when unused. This can be re-configured to GPIO12. |
| LDO_1V5 | 37 | O | — | Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This pin cannot source current to external circuits. |
| LDO_3V3 | 34 | O | — | Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with capacitance CLDO_3V3 to GND. |
| PA_CC1 | 31 | I/O | Hi-Z | I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to GND (CPx_CCy). |
| PA_CC2 | 30 | I/O | Hi-Z | I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to GND (CPx_CCy). |
| PA_GATE_VSYS | 5 | O | Hi-Z | Connect to the PortA N-ch MOSFET that has source tied to VSYS. |
| PA_GATE_VBUS | 19 | O | Hi-Z | Connect to the N-ch MOSFET that has source tied to PA_VBUS. |
| PA_VBUS | 21,22,23,24 | I/O | — | 5-V to 20-V input or 5-V output from PP5V. Bypass with capacitance CVBUS to GND. |
| PB_CC1 | 6 | I/O | Hi-Z | I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to GND (CPx_CCy). |
| PB_CC2 | 7 | I/O | Hi-Z | I/O for USB Type-C and USB PD. Filter noise with recommended capacitor to GND (CPx_CCy). |
| PB_GATE_VSYS | 4 | O | Hi-Z | Connect to the Port B N-ch MOSFET that has source tied to VSYS. |
| PB_GATE_VBUS | 18 | O | Hi-Z | Connect to the N-ch MOSFET that has source tied to PB_VBUS. |
| PB_VBUS | 13,14,15,16 | I/O | — | 5-V to 20-V input or 5-V output from PP5V. Bypass with capacitance CVBUS to GND. |
| PP5V | 11,12,17,20,25,26 | I | — | 5-V System Supply to VBUS, supply for Px_CCy pins as VCONN. |
| VSYS | 3 | I | — | High-voltage sinking node in the system. It is used to implement reverse-current-protection (RCP) for the external sinking paths controlled by PA_GATE_VSYS and PB_GATE_VSYS. |
| VIN_3V3 | 32 | I | — | Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. |