国产顶级熟妇高潮XXXXX,卡一卡二卡三国产拍

ZHCSSL6C July 2023 – April 2024 TPS7H6003-SP , TPS7H6013-SP , TPS7H6023-SP

PRODUCTION DATA

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

HBX|48

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7.5 Electrical Characteristics

Specifications are over ambient temperature operating range T_A = –55°C to 125°C, VIN = 10 V to 14 V, V_BP5L= V_BP5H= 5 V, and no load on LOH, LOL, HOH, and HOL (unless otherwise noted).

PARAMETER		TEST CONDITIONS		SUBGROUP⁽¹⁾	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_QLS	Low-side quiescent current	VIN = 12 V, BOOT = 10 V	MODE = PWM, EN = 0 V	1, 2, 3		5	6.8	mA
I_QLS	Low-side quiescent current	VIN = 12 V, BOOT = 10 V	MODE = IIM, LI = HI = 0 V	1, 2, 3		5	8	mA
I_QHS	High-side quiescent current	VIN = 12 V, BOOT = 10 V	MODE = PWM, EN = 0 V	1, 2, 3		4	6.3	mA
I_QHS	High-side quiescent current	VIN = 12 V, BOOT = 10 V	MODE = IIM, LI = HI = 0 V	1, 2, 3		4	6.3	mA
I_QBG	BOOT to AGND quiescent current (TPS7H6003-SP)	SW = 100 V, BOOT = 110 V				20		μA
I_QBG	BOOT to AGND quiescent current (TPS7H6013-SP)	SW = 28 V, BOOT = 38 V				15		μA
I_QBG	BOOT to AGND quiescent current (TPS7H6023-SP)	SW = 12 V, BOOT = 22 V				10		μA
I_{OP_BG}	BOOT to AGND operating current (TPS7H6003-SP)	SW = 100 V, BOOT = 110 V				20		μA
I_{OP_BG}	BOOT to AGND operating current (TPS7H6013-SP)	SW = 28 V, BOOT = 38 V				15		μA
I_{OP_BG}	BOOT to AGND operating current (TPS7H6023-SP)	SW = 12 V, BOOT = 22 V				10		μA
I_{OP_LS}	Low-side operating current	MODE = PWM, no load for LOL and LOH	f = 500 kHz	1, 2, 3		6	9	mA
			f = 1 MHz	1, 2, 3		8	11
			f = 2 MHz	1, 2, 3		12	16
			f = 5 MHz	1, 2, 3		20	30
		MODE = IIM, no load for LOL and LOH	f = 500 kHz	1, 2, 3		6	9
			f = 1 MHz	1, 2, 3		8	12
			f = 2 MHz	1, 2, 3		11	17
			f = 5 MHz	1, 2, 3		20	30
I_{OP_HS}	High-side operating current	MODE = PWM, no load for HOL and HOH	f = 500 kHz	1, 2, 3		5	6.5	mA
			f = 1 MHz	1, 2, 3		5.3	8
			f = 2 MHz	1, 2, 3		7	10.5
			f = 5 MHz	1, 2, 3		13	17.5
		MODE = IIM, no load for HOL and HOH	f = 500 kHz	1, 2, 3		4.5	6.5
			f = 1 MHz	1, 2, 3		5.3	8
			f = 2 MHz	1, 2, 3		7	10.5
			f = 5 MHz	1, 2, 3		11.7	15
LOW-SIDE TO HIGH-SIDE CAPACITANCE
	Low-side to high-side capacitance	Low-side pins shorted together and high-side pins shorted together				6		pF
GATE DRIVER
V_OL	Low-level output voltage	I_OL = 100 mA		1, 2, 3		0.07	0.15	V
BP5x – V_OH	High-level output voltage	I_OH = 100 mA		1, 2, 3		0.13	0.3	V
I_OH	Peak source current	HOH, LOH = 0 V, BP5x = 5 V		1, 2, 3	0.7	1.3	2.3	A
I_OL	Peak sink current	HOL, LOL = 5 V, BP5x = 5 V		1, 2, 3	1.6	2.5	4.6	A
INTERNAL REGULATORS
V_BP5L	Low-side 5-V regulator output voltage	C_BP5L = 1 μF		1, 2, 3	4.75	5.0	5.175	V
	Required BP5L output capacitor ⁽²⁾			1, 2, 3	1			μF
V_BP5H	High-side 5-V regulator output voltage	C_BP5H = 1 μF		1, 2, 3	4.75	5.0	5.175	V
	Required BP5H output capacitor ⁽²⁾				1			μF
V_BP7L	7-V regulator output voltage			1, 2, 3	6.65	7	7.35	V
	Required BP7L output capacitor ⁽²⁾				1			μF
UNDERVOLTAGE PROTECTION
BP5H_R	BP5H UVLO rising threshold	C_BP5H = 1 μF		1, 2, 3	4.0	4.25	4.5	V
BP5H_F	BP5H UVLO falling threshold	C_BP5H = 1 μF		1, 2, 3	3.8	4.05	4.3
BP5H_H	BP5H UVLO hysteresis	C_BP5H = 1 μF				0.2
BP5L_R	BP5L UVLO rising threshold	C_BP5L = 1 μF		1, 2, 3	4.0	4.25	4.5	V
BP5L_F	BP5L UVLO falling threshold	C_BP5L = 1 μF		1, 2, 3	3.8	4.05	4.3
BP5L_H	BP5L UVLO hysteresis	C_BP5L = 1 μF				0.2
BP7L_R	BP7L UVLO rising threshold	C_BP7L = 1 μF		1, 2, 3	6.2	6.5	6.8	V
BP7L_F	BP7L UVLO falling threshold	C_BP7L = 1 μF		1, 2, 3	5.9	6.2	6.5
BP7L_H	BP7L UVLO hysteresis	C_BP7L = 1 μF				0.3
VIN_R	VIN UVLO rising threshold			1, 2, 3	8.0	8.6	9.0	V
VIN_F	VIN UVLO falling threshold			1, 2, 3	7.5	8.1	8.5
VIN_H	VIN UVLO hysteresis					0.53
BOOT_R	BOOT UVLO rising threshold			1, 2, 3	6.6	7.1	7.4	V
BOOT_F	BOOT UVLO falling threshold			1, 2, 3	6.2	6.65	7
BOOT_H	BOOT UVLO hysteresis					0.45
INPUT PINS
V_IR	Input rising edge threshold			1, 2, 3	1.80		2.65	V
V_IF	Input falling edge threshold			1, 2, 3	1.15		1.85	V
V_IHYS	Input hysteresis					0.8		V
R_PD	Input pull-down resistance	V = 2.15 V applied at input (EN_HI or PWM_LI)		1, 2, 3	100		400	k?
PROGRAMMBLE DEAD TIME
T_DLH	LO off to HO on dead time	MODE = PWM, LO falling to HO rising (90% to 10%), f ≤ 2 MHz	RLH = 3.32 k?	9, 10 , 11	0	4.5	10	ns
			RLH = 11.8 k?	9, 10 , 11	8	12	15.5
			RLH = 21 k?	9, 10 , 11	15.5	21	24
			RLH = 52.3 k?	9, 10 , 11	36	50	59
			RLH = 105 k?	9, 10 , 11	74	97	113.5
T_DHL	HO off to LO on dead time	MODE = PWM, HO falling to LO rising (90% to 10%), f ≤ 2 MHz	RHL = 7.87 k?	9, 10 , 11	0	5	10	ns
			RHL = 13.3 k?	9, 10 , 11	6	10.5	15
			RHL = 23.7 k?	9, 10 , 11	16	21	24.5
			RHL = 57.6 k?	9, 10 , 11	44	53	61
			RHL = 113 k?	9, 10 , 11	86	105	125
BOOTSTRAP DIODE SWITCH
R_{BST_SW}	Bootstrap diode switch resistance	I_{BST_SW} = 100 mA		1, 2, 3		0.43		?
	Bootstrap diode switch parallel resistance	I_{BST_RP} = 1 mA		1, 2, 3	0.8	1	1.2	k?
POWER GOOD
	Logic-low output	I_FLT = 1 mA		1, 2, 3			0.4	V
	PGOOD internal resistance	BP5L = 5 V, BP7L = 7 V, VIN = 12 V		1, 2, 3	0.7	1	1.9	M?
	Minimum BP5L voltage for valid PGOOD output			1, 2, 3		2	2.45	V

(1) Subgroups are applicable for QML parts. For subgroup definitions, see Quality Conformance Inspection.

(2) Specified by design; not tested in production.