SLLS519J March 2002 – July 2017 TUSB3410
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLKOUT | 22 | O | Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see (1) and Section 5.5.5.5) |
CTS | 13 | I | UART: Clear to send(4) |
DCD | 15 | I | UART: Data carrier detect(4) |
DM | 7 | I/O | Upstream USB port differential data minus |
DP | 6 | I/O | Upstream USB port differential data plus |
DSR | 14 | I | UART: Data set ready(4) |
DTR | 21 | O | UART: Data terminal ready(1) |
GND | 8, 18, 28 | GND | Digital ground |
P3.0 | 32 | I/O | General-purpose I/O 0 (port 3, terminal 0)(3)(5)(8) |
P3.1 | 31 | I/O | General-purpose I/O 1 (port 3, terminal 1)(3)(5)(8) |
P3.3 | 30 | I/O | General-purpose I/O 3 (port 3, terminal 3)(3)(5)(8) |
P3.4 | 29 | I/O | General-purpose I/O 4 (port 3, terminal 4)(3)(5)(8) |
PUR | 5 | O | Pullup resistor connection(2) |
RESET | 9 | I | Device master reset input(4) |
RI/CP | 16 | I | UART: Ring indicator(4) |
RTS | 20 | O | UART: Request to send(1) |
SCL | 11 | O | Master I2C controller: clock signal(1) |
SDA | 10 | I/O | Master I2C controller: data signal(1)(5) |
SIN/IR_SIN | 17 | I | UART: Serial input data / IR Serial data input(6) |
SOUT/IR_SOUT | 19 | O | UART: Serial output data / IR Serial data output(7) |
SUSPEND | 2 | O | Suspend indicator terminal(3). When this terminal is asserted high, the device is in suspend mode. |
TEST0 | 23 | I | Test input (for factory test only). This terminal must be tied to VCC through a 10-kΩ resistor. |
TEST1 | 24 | I | Test input (for factory test only)(5). This terminal must be tied to VCC through a 10-kΩ resistor. |
VCC | 3, 25 | PWR | 3.3 V |
VDD18 | 4 | PWR | 1.8-V supply. An internal voltage regulator generates this supply voltage when terminal VREGEN is low. When VREGEN is high, 1.8 V must be supplied externally. |
VREGEN | 1 | I | This active-low terminal is used to enable the 3.3-V to 1.8-V voltage regulator. |
WAKEUP | 12 | I | Remote wake-up request terminal. When low, wakes up system(5) |
X1/CLKI | 27 | I | 12-MHz crystal input or clock input |
X2 | 26 | O | 12-MHz crystal output |