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SLLS519J March 2002 – July 2017 TUSB3410

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

VF|32
- MTQF002C
RHB|32
- MPQF130D

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- QFND029X

訂購信息

slls519j_pm

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		−0.5	3.6	V
V_I	Input voltage		−0.5	V_CC + 0.5	V
V_O	Output voltage		−0.5	V_CC + 0.5	V
I_IK	Input clamp current			±20	mA
I_OK	Output clamp current			±20	mA
T_stg	Storage temperature	Industrial	–65	150	°C
T_stg	Storage temperature	Standard	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

				VALUE	UNIT
V_ESD	Electrostatic discharge (ESD) performance	Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾		±2000	V
V_ESD	Electrostatic discharge (ESD) performance	Charged Device Model (CDM), per JESD22-C101⁽²⁾	All pins	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

			MIN	TYP	MAX	UNIT
V_CC	Supply voltage		3	3.3	3.6	V
V_I	Input voltage		0		V_CC	V
V_IH	High-level input voltage	TTL	2		V_CC	V
V_IH	High-level input voltage	CMOS	0.7 × V_CC		V_CC	V
V_IL	Low-level input voltage	TTL	0		0.8	V
V_IL	Low-level input voltage	CMOS	0		0.2 × V_CC	V
T_A	Operating temperature	Commercial range	0		70	°C
T_A	Operating temperature	Industrial range	–40		85	°C

4.4 Thermal Information

THERMAL METRIC⁽¹⁾		TUSB3410		UNIT
		RHB (VQFN)	VF (LQFP)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	32.1	70.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	24.6	31.4	°C/W
R_θJB	Junction-to-board thermal resistance	6.5	28.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	2.2	°C/W
ψ_JB	Junction-to-board characterization parameter	6.5	28.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	24.6	31.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application report.

4.5 Electrical Characteristics

T_A = 25°C, V_CC = 3.3 V ±5%, V_SS = 0 V

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	TTL	I_OH = –4 mA	V_CC – 0.5			V
V_OH	High-level output voltage	CMOS	I_OH = –4 mA	V_CC – 0.5			V
V_OL	Low-level output voltage	TTL	I_OL = 4 mA			0.5	V
V_OL	Low-level output voltage	CMOS	I_OL = 4 mA			0.5	V
V_IT+	Positive threshold voltage	TTL	V_I = V_IH			1.8	V
V_IT+	Positive threshold voltage	CMOS	V_I = V_IH			0.7 × V_CC	V
V_IT−	Negative threshold voltage	TTL	V_I = V_IH	0.8		1.8	V
V_IT−	Negative threshold voltage	CMOS	V_I = V_IH	0.2 × V_CC			V
V_hys	Hysteresis (V_IT+ − V_IT−)	TTL	V_I= V_IH	0.3		0.7	V
V_hys	Hysteresis (V_IT+ − V_IT−)	CMOS	V_I= V_IH	0.17 × V_CC		0.3 × V_CC	V
I_IH	High-level input current	TTL	V_I = V_IH			±20	µA
I_IH	High-level input current	CMOS	V_I = V_IH			±1	µA
I_IL	Low-level input current	TTL	V_I = V_IL			±20	µA
I_IL	Low-level input current	CMOS	V_I = V_IL			±1	µA
I_OZ	Output leakage current (Hi-Z)		V_I = V_CCor V_SS			±20	µA
I_OL	Output low drive current			0.1			mA
I_OH	Output high drive current			0.1			mA
I_CC	Supply current (operating)		Serial data at 921.6 k			15	mA
I_CC	Supply current (suspended)					200	µA
	Clock duty cycle⁽¹⁾				50%
	Jitter specification⁽¹⁾					±100	ppm
C_I	Input capacitance					18	pF
C_O	Output capacitance					10	pF

(1) Applies to all clock outputs

4.6 Timing and Switching Characteristics Information

4.6.1 Wakeup Timing (WAKEUP or RI/CP Transitions)

The TUSB3410 device can be brought out of the suspended state, or woken up, by a command from the host. The TUSB3410 device also supports remote wakeup and can be awakened by either of two input signals. A low pulse on the WAKEUP terminal or a low-to-high transition on the RI/CP terminal wakes up the device.

NOTE

For reliable operation, either condition must persist for approximately 3-ms minimum, which allows time for the crystal to power up because in the suspend mode, the crystal interface is powered down. The state of the WAKEUP or RI/CP terminal is then sampled by the clock to verify there was a valid wake-up event.

4.6.2 Reset Timing

There are three requirements for the reset signal timing. First, the minimum reset pulse duration is 100 μs. At power up, this time is measured from the time the power ramps up to 90% of the nominal V_CC until the reset signal exceeds 1.2 V. The second requirement is that the clock must be valid during the last 60 µs of the reset window. The third requirement is that, according to the USB specification, the device must be ready to respond to the host within 100 ms. This means that within the 100-ms window, the device must come out of reset, load any pertinent data from the I²C EEPROM device, and transfer execution to the application firmware if any is present. Because the latter two events can require significant time, the amount of which can change from system to system, TI recommends having the device come out of reset within 30 ms, leaving 70 ms for the other events to complete. This means the reset signal must rise to
1.8 V within 30 ms.

These requirements are depicted in Figure 4-1. When using a 12-MHz crystal, the clock signal may take several milliseconds to ramp up and become valid after power up. Therefore, the reset window may need to be elongated up to 10 ms or more to ensure that there is a 60-µs overlap with a valid clock.

Figure 4-1 Reset Timing

4.7 Typical Characteristics

Figure 4-2 Supply Current at 3 V

Figure 4-4 Supply Current at 3.6 V

Figure 4-3 Supply Current at 3.3 V