ZHCSIJ8A July 2018 – October 2021 TPS3431-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRB|8
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DRB|8
訂購(gòu)信息
8.2.2.1 Calculating WDO Pullup Resistor Design 1
The TPS3431-Q1 uses an open-drain configuration for the WDO circuit, as shown in Figure 8-3. When the internal MOSFET is off, the external pull-up resistor pulls the drain of the transistor to VDD and when the MOSFET is turned on, the MOSFET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below the maximum value.
To choose the proper pull-up resistor, there are three key specifications to keep in mind: the pull-up voltage (VPU), the recommended maximum WDO pin current (IWDO), and VOL.
The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.4 V with IWDO kept below 10 mA. For this example, with a VPU of 3.3 V, a resistor must be chosen to keep IWDO below 35 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pull-up resistor value of 100 kΩ was selected, which sinks a maximum of 33 μA when WDO is asserted.
Figure 8-3 WDO Open-Drain Configuration