Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-μF ceramic capacitor as near as possible to the VDD pin.
If a CCWD capacitor or pull-up resistor is used, place these components as close as possible to the CWD pin. If the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
Place the pull-up resistor on
WDO as close to the pin as possible.