ZHCSM96A November 2020 – August 2021 TPS6521835
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.3.1.1 Power-Up Sequencing
- 7.3.1.2 Power-Down Sequencing
- 7.3.1.3 Strobe 1 and Strobe 2
- 7.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
- 7.3.1.5 Backup Supply Power-Good (PGOOD_BU)
- 7.3.1.6 Internal LDO (INT_LDO)
- 7.3.1.7 Current Limited Load Switches
- 7.3.1.8 LDO1
- 7.3.1.9 Coin Cell Battery Voltage Acquisition
- 7.3.1.10 UVLO
- 7.3.1.11 Power-Fail Comparator
- 7.3.1.12 Battery-Backup Supply Power-Path
- 7.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
- 7.3.1.14 I/O Configuration
- 7.3.1.15 Push Button Input (PB)
- 7.3.1.16 AC_DET Input (AC_DET)
- 7.3.1.17 Interrupt Pin (INT)
- 7.3.1.18 I2C Bus Operation
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSL|48
訂購(gòu)信息
5 Pin Configuration and Functions
#X5492 shows the 48-pin RSL Plastic Quad Flatpack No-Lead.
Figure 5-1 48-Pin RSL VQFN With Exposed Thermal Pad (Top View, 6 mm × 6 mm × 1 mm With
0.4-mm Pitch)Table 5-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | IN_DCDC1 | P | Input supply pin for DCDC1. |
| 2 | SDA | I/O | Data line for the I2C interface. Connect to pullup resistor. |
| 3 | SCL | I | Clock input for the I2C interface. Connect to pullup resistor. |
| 4 | LDO1 | O | Output voltage pin for LDO1. Connect to capacitor. |
| 5 | IN_LDO1 | P | Input supply pin for LDO1. |
| 6 | IN_LS3 | P | Input supply pin for load switch 3. |
| 7 | LS3 | O | Output voltage pin for load switch 3. Connect to capacitor. |
| 8 | PGOOD | O | Power-good output (configured as open drain). Pulled low when either DCDC1-4 or LDO1 are out of regulation. Load switches and DCDC5-6 do not affect PGOOD pin. |
| 9 | AC_DET | I | AC monitor input and enable for DCDC1-4, LDO1 and load switches. See GUID-C40D3B3A-86FC-4310-8897-D3A71A45FE30.html#GUID-C40D3B3A-86FC-4310-8897-D3A71A45FE30 for details. Tie pin to IN_BIAS if not used. |
| 10 | nPFO | O | Power-fail comparator output, deglitched (open drain). Pin is pulled low when PFI input is below power-fail threshold. |
| 11 | GPIO1 | I/O | Pin configured as DDR reset-input (driving GPO2) or as general-purpose, open-drain output. See GUID-95DCE928-CFE8-4BC5-8DFF-BE7F13DCFD84.html#GUID-95DCE928-CFE8-4BC5-8DFF-BE7F13DCFD84 for more information. |
| 12 | IN_DCDC4 | P | Input supply pin for DCDC4. |
| 13 | L4A | P | Switch pin for DCDC4. Connect to inductor. |
| 14 | L4B | P | Switch pin for DCDC4. Connect to inductor. |
| 15 | DCDC4 | P | Output voltage pin for DCDC4. Connect to capacitor. |
| 16 | PFI | I | Power-fail comparator input. Connect to resistor divider. |
| 17 | DC34_SEL | I | Power-up default selection pin for DCDC3 or DCDC4. Power-up default is programmed by a resistor connected to ground. See GUID-0ACB1843-781C-43C2-A01A-911960C64E9A.html#GUID-0ACB1843-781C-43C2-A01A-911960C64E9A for resistor options. |
| 18 | IN_nCC | O | Output pin indicates if DCDC5 and DCDC6 are powered from main supply (IN_BU) or coin-cell battery (CC). Pin is push-pull output. Pulled low when PMIC is powered from coin cell battery. Pulled high when PMIC is powered from main supply (IN_BU). |
| 19 | PGOOD_BU | O | Power-good, push-pull output for DCDC5 and DCDC6. Pulled low when either DCDC5 or DCDC6 is out of regulation. Pulled high (to DCDC6 output voltage) when both rails are in regulation. |
| 20 | L5 | P | Switch pin for DCDC5. Connect to inductor. |
| 21 | FB5 | I | Feedback voltage pin for DCDC5. Connect to output capacitor. |
| 22 | FB6 | I | Feedback voltage pin for DCDC6. Connect to output capacitor. |
| 23 | L6 | P | Switch pin for DCDC6. Connect to inductor. |
| 24 | SYS_BU | P | System voltage pin for battery-backup supply power path. Connect to 1-μF capacitor. Connecting any external load to this pin is not recommended. |
| 25 | CC | P | Coin cell battery input. Serves as the supply to DCDC5 and DCDC6 if no voltage is applied to IN_BU. Tie this pin to ground if it is not in use. |
| 26 | GPIO3 | I/O | Pin can be configured as warm reset (negative edge) for DCDC1 and DCDC2 or as a general-purpose, open-drain output. See GUID-95DCE928-CFE8-4BC5-8DFF-BE7F13DCFD84.html#GUID-95DCE928-CFE8-4BC5-8DFF-BE7F13DCFD84 for more details. |
| 27 | IN_BU | P | Default input supply pin for battery backup supplies (DCDC5 and DCDC6). |
| 28 | N/C | — | No connect. Leave pin floating. |
| 29 | N/C | ||
| 30 | LS1 | O | Output voltage pin for load switch 1. Connect to capacitor. |
| 31 | IN_LS1 | P | Input supply pin for load switch 1. |
| 32 | IN_LS2 | P | Input supply pin for load switch 2. |
| 33 | LS2 | O | Output voltage pin for load switch 2. Connect to capacitor. |
| 34 | GPO2 | O | Pin configured as DDR reset signal (controlled by GPIO1) or as general-purpose output. Buffer can be configured as push-pull or open-drain. |
| 35 | INT_LDO | P | Internal bias voltage. Connecting any external load to this pin is not recommended. |
| 36 | IN_BIAS | P | Input supply pin for reference system. |
| 37 | IN_DCDC3 | P | Input supply pin for DCDC3. |
| 38 | L3 | P | Switch pin for DCDC3. Connect to inductor. |
| 39 | FB3 | I | Feedback voltage pin for DCDC3. Connect to output capacitor. |
| 40 | nWAKEUP | O | Signal to SOC to indicate a power on event (active low, open-drain output). |
| 41 | FB2 | I | Feedback voltage pin for DCDC2. Connect to output capacitor. |
| 42 | L2 | P | Switch pin for DCDC2. Connect to inductor. |
| 43 | IN_DCDC2 | P | Input supply pin for DCDC2. |
| 44 | PB | I | Push-button monitor input. Typically connected to a momentary switch to ground (active low). See GUID-C40D3B3A-86FC-4310-8897-D3A71A45FE30.html#GUID-C40D3B3A-86FC-4310-8897-D3A71A45FE30 for details. |
| 45 | nINT | O | Interrupt output (active low, open drain). Pin is pulled low if an interrupt bit is set. The pin returns to Hi-Z state after the bit causing the interrupt has been read. Interrupts can be masked. |
| 46 | PWR_EN | I | Power enable input for DCDC1-4, LDO1 and load switches. See GUID-C40D3B3A-86FC-4310-8897-D3A71A45FE30.html#GUID-C40D3B3A-86FC-4310-8897-D3A71A45FE30 for details. |
| 47 | FB1 | I | Feedback voltage pin for DCDC1. Connect to output capacitor. |
| 48 | L1 | P | Switch pin for DCDC1. Connect to inductor. |
| — | Thermal Pad | P | Power ground and thermal relief. Connect to ground plane. |