Abstract

This application report investigates the impact of the printed circuit board (PCB) layout on low dropout (LDO) regulator thermal performance, specifically the junction-to-ambient thermal resistance, θ_JA. This parameter is measured for the TPS745 (WSON package), TPS7B82-Q1 (TO-252 package), and TLV755P (SOT-23 package) devices. Each device is tested with five layouts, each containing increasing amounts of copper coverage on both internal and external layers. Increasing the amount of copper coverage reduces θ_JA, but reaches a point of diminishing returns. Copper coverage is more effective on packages with thermal pads. These results are used to provide layout tips for system designers to improve thermal performance. Although the devices tested in this study are exclusively LDOs, the effects of the PCB layout and conclusions drawn in this application report are extended to other power dissipative devices.