4 Conclusion

The thermal performance of the LDO in terms of its junction-to-ambient thermal resistance, θ_JA, is highly dependent on the PCB design. However, the impact of the PCB is ultimately limited by the package of the LDO. Packages with thermal pads, like the WSON and TO-252 packages, are more thermally dissipative and, therefore, see a larger overall reduction in θ_JA at 74% and 71% respectively when compared to the worst-case 1S0P approximation layout. The SOT-23 package sees a smaller, but still significant, reduction at 54%. Figure 3-5 illustrates that θ_JA can be reduced between 32% and 55% with a thermally optimized layout compared to the data sheet specifications. This result indicates that using the datasheet specified θ_JA for thermal calculations provides a conservative estimate of thermal performance. However, a designer must keep in mind that a thermally efficient layout allows for a higher operating ambient temperature, a higher level of power dissipation, or some combination of these two advantages.

Figure 3-6 shows that regardless of package type, thermal performance saturates as copper content in the PCB increases. For all three packages, The Thermally Enhanced layout contained about half the copper area of the Thermally Saturated layout, but provided a θ_JA within 8%. Similarly, the improvement in thermal performance due to additional thermal vias also saturates. Stitching additional vias through the PCB yields little benefit as seen from the Thermally Saturated layouts. A design with sufficient thermal performance can be achieved with a layout similar to the Thermally Enhanced board. For more compact designs, see Figure 3-4, which show the results from the TLV755P (SOT-23) measurements. These results indicate that copper must be maximized on the top and bottom layers as these layers are not surrounded by additional PCB material and are therefore the most effective for heat dissipation. Additional thermal vias only need to be included around the device to effectively spread the heat generated by the LDO to other copper layers. These vias are especially critical when designing with packages that do not have a thermal pad, like the SOT-23 package. In these cases, thermal vias can also be placed directly under the device where the most heat is generated. Packages with thermal pads maximize the amount of thermal vias in the landing pad according to https://www.jedec.org/system/files/docs/JESD51-9.pdf. Lastly, data from all Internally Disconnected layouts Figure 3-6 show that additional copper on internal layers must be included if possible and have a positive impact on thermal performance, even if not directly connected to the LDO.