ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Programming
- 8.5
Register Maps
- 8.5.1
Control and Status Registers Overview
- 8.5.1.1 CSR Bit Field Definitions – ID Registers
- 8.5.1.2 CSR Bit Field Definitions – Reset and Clock Registers
- 8.5.1.3 CSR Bit Field Definitions – DSI Registers
- 8.5.1.4 CSR Bit Field Definitions – LVDS Registers
- 8.5.1.5
CSR Bit Field Definitions – Video Registers
- 8.5.1.5.1 Register 0x20
- 8.5.1.5.2 Register 0x21
- 8.5.1.5.3 Register 0x24
- 8.5.1.5.4 Register 0x25
- 8.5.1.5.5 Register 0x28
- 8.5.1.5.6 Register 0x29
- 8.5.1.5.7 Register 0x2C
- 8.5.1.5.8 Register 0x2D
- 8.5.1.5.9 Register 0x30
- 8.5.1.5.10 Register 0x31
- 8.5.1.5.11 Register 0x34
- 8.5.1.5.12 Register 0x36
- 8.5.1.5.13 Register 0x38
- 8.5.1.5.14 Register 0x3A
- 8.5.1.5.15 Register 0x3C
- 8.5.1.6 CSR Bit Field Definitions – IRQ Registers
- 8.5.1
Control and Status Registers Overview
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PAP|64
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- PAP|64
訂購信息
7 Parameter Measurement Information
Figure 1. DSI HS Mode Receiver Timing Definitions 
Figure 2. DSI Receiver Voltage Definitions 
Figure 3. Test Load and Voltage Definitions for LVDS Outputs 
Figure 4. SN65DSI83-Q1 LVDS Timing Definitions 
1. See the ULPS section of the data sheet for the ULPS entry and exit sequence.
2. ULPS entry and exit protocol and timing requirements must be met according to the MIPI DPHY specification.
Figure 5. ULPS Timing Definition