ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
The video resolution parameters required by the panel need to be programmed into the SN65DSI83-Q1 device. For this example, the parameters programmed are the following:
Horizontal Active = 1280 or 0×500
CHA_ACTIVE_LINE_LENGTH_LOW = 0×00
CHA_ACTIVE_LINE_LENGTH_HIGH = 0×05
Vertical Active = 800 or 0×320
CHA_VERTICAL_DISPLAY_SIZE_LOW = 0×20
CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0×03
Horizontal Pulse Width = 128 or 0×80
CHA_HSYNC_PULSE_WIDTH_LOW = 0×80
CHA_HSYNC_PULSE_WIDTH_HIGH = 0×00
Vertical Pulse Width = 7
CHA_VSYNC_PULSE_WIDTH_LOW = 0×07
CHA_VSYNC_PULSE_WIDTH_HIGH = 0×00
Horizontal Backporch = HorizontalBlanking – (HorizontalSyncOffset + HorizontalSyncPulseWidth)
Horizontal Backporch = 384 – (64 + 128)
Horizontal Backporch = 192 or 0×C0
CHA_HORIZONTAL_BACK_PORCH = 0×C0
Vertical Backporch = VerticalBlanking – (VerticalSyncOffset +VerticalSyncPulseWidth)
Vertical Backporch = 30 – (3 + 7)
Vertical Backporch = 20 or 0×14
CHA_VERTICAL_BACK_PORCH = 0×14
Horizontal Frontporch = HorizontalSyncOffset
Horizontal Frontporch = 64 or 0×40
CHA_HORIZONTAL_FRONT_PORCH = 0×40
Vertical Frontporch = VerticalSyncOffset
Vertical Frontporch = 3
CHA_VERTICAL_FRONT_PORCH = 0×03
The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0×3C and configuring the TEST PATTERN GENERATION PURPOSE ONLY register as shown in Table 30.
LVDS clock is derived from the DSI channel A clock. When the MIPI D-PHY channel A HS clock is used as the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0×0B.7:3) to generate the LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0×0A.3:1) and CH_DSI_CLK_RANGE(CSR 0×12) must be set to the frequency range of the LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0×0D.0) must be set to enable the internal PLL.
LVDS_CLK_RANGE = 2 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A
DSI_CLK_DIVIDER = 00101 – Divide by 6
CHA_DSI_LANES = 00 – Four lanes are enabled
CHA_DSI_CLK_RANGE = 0×64 – 500 MHz