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ZHCSFF4C February 2016 – August 2021 TPS65981

PRODUCTION DATA

封裝選項

請參考 PDF 數(shù)據表獲取器件具體的封裝圖。

機械數(shù)據 (封裝 | 引腳)

RTQ|56

散熱焊盤機械數(shù)據 (封裝 | 引腳)

訂購信息

7.19 Input-Output (I/O) Requirements and Characteristics

Recommended operating conditions; T_A = –40°C to +105°C unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SPI
SPI_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
SPI_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
SPI_HYS	Input hysteresis voltage	LDO_3V3 = 3.3 V	0.2			V
SPI_ILKG	Leakage current	Output is Hi-Z, V_IN = 0 to LDO_3V3	–1		1	μA
SPI_VOH	SPI output-high voltage	I_O = –8 mA, LDO_3V3=3.3 V	2.9			V
SPI_VOH	SPI output-high voltage	I_O = –15 mA, LDO_3V3=3.3 V	2.5			V
SPI_VOL	SPI output-low voltage	I_O = 10 mA			0.4	V
SPI_VOL	SPI output-low voltage	I_O = 20 mA			0.8	V
SWDIO
SWDIO_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
SWDIO_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
SWDIO_HYS	Input hysteresis voltage	LDO_3V3 = 3.3 V	0.2			V
SWDIO_ILKG	Leakage current	Output is Hi-Z, V_IN = 0 to LDO_3V3	–1		1	μA
SWDIO_VOH	Output high voltage	I_O = –8 mA, LDO_3V3 = 3.3 V	2.9			V
SWDIO_VOH	Output high voltage	I_O = –15 mA, LDO_3V3 = 3.3 V	2.5			V
SWDIO_VOL	Output low voltage	I_O = 10 mA			0.4	V
SWDIO_VOL	Output low voltage	I_O = 20 mA			0.8
SWDIO_RPU	Pull-up resistance		2.8	4	5.2	kΩ
SWDIO_TOS	SWDIO output skew to falling edge SWDCLK		–5		5	ns
SWDIO_TIS	Input setup time required between SWDIO and rising edge of SWCLK		6			ns
SWDIO_TIH	Input hold time required between SWDIO and rising edge of SWCLK		1			ns
SWDCLK
SWDCL_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
SWDCL_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
SWDCL_THI	SWDIOCLK HIGH period		0.05		500	μs
SWDCL_TLO	SWDIOCLK LOW period		0.05		500	μs
SWDCL_HYS	Input hysteresis voltage	LDO_3V3 = 3.3 V	0.2			V
SWDCL_RPU	Pull-up resistance		2.8	4	5.2	kΩ
GPIO (GPIO0, GPIO2-8, DEBUG1, DEBUG_CTL1/2, MRESET, RESETZ, BUSPOWERZ)
GPIO_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
GPIO_VIH	High-level input voltage	VDDDIO = 1.8 V	1.25			V
GPIO_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
GPIO_VIL	Low-level input voltage	VDDIO = 1.8 V			0.63	V
GPIO_HYS	Input hysteresis voltage	LDO_3V3 = 3.3 V	0.2			V
GPIO_HYS	Input hysteresis voltage	VDDIO = 1.8 V	0.09			V
GPIO_ILKG	I/O leakage current	Pin is Hi-Z; V_IN = 0 V to VDD (VDDIO or LDO_3V3)	–1		1	μA
GPIO_RPU	Pull-up resistance (GPIO0, GPIO2-8, DEBUG1, MRESET, RESETZ, BUSPOWERZ)	Pull-up enabled	50	100	150	k?
GPIO_RPU	Pull-up resistance (DEBUG_CTL1/2)	Pull-up enabled	2.5	5	7.5	k?
GPIO_RPD	Pull-down resistance (GPIO0, GPIO2-8, DEBUG1, MRESET, RESETZ, BUSPOWERZ)⁽¹⁾	Pull-down enabled	50	100	150	k?
GPIO_DG	Digital input path de-glitch			20		ns
GPIO_VOH	GPIO output-high voltage	I_O = –2 mA, LDO_3V3 = 3.3 V	2.9			V
GPIO_VOH	GPIO output-high voltage	I_O = –2 mA, VDDIO = 1.8 V	1.35			V
GPIO_VOL	GPIO output-low voltage	I_O = 2 mA, LDO_3V3 = 3.3 V			0.4	V
GPIO_VOL	GPIO output-low voltage	I_O = 2 mA, VDDIO = 1.8 V			0.45	V
I2C_IRQZ
OD_VOL	Low-level output voltage	I_OL = 2 mA			0.4	V
OD_LKG	Leakage current	Output is Hi-Z, V_IN = 0 to LDO_3V3	–1		1	μA
SBU
SBU_VIH	High-level input voltage	LDO_3V3 = 3.3 V	2			V
SBU_VIL	Low-level input voltage	LDO_3V3 = 3.3 V			0.8	V
SBU_HYS	Input hysteresis voltage	LDO_3V3 = 3.3 V	0.2			V

(1) DEBUG_CTL1/2 do not have an internal pull-down resistance path.