產(chǎn)品詳情

Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2020 Architecture Folding Interpolating SNR (dB) 60.4 ENOB (Bits) 9.7 SFDR (dB) 74.3 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500, 1000 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2020 Architecture Folding Interpolating SNR (dB) 60.4 ENOB (Bits) 9.7 SFDR (dB) 74.3 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm2 27 x 27
  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 1.6/1.0 GSPS Interleaved or 800/500 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 1.6/1.0 GSPS ADCIMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61 dBc (typ)IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69 dBc (typ)Noise Floor: -152.2/-150.5 dBm/Hz (typ)Noise Power Ratio: 50.4/50.7 dB (typ)Power: 2.50/2.02 W (typ)
    • Dual 800/500 MSPS ADC, Fin = 498 MHzENOB: 9.5/9.6 Bits (typ)SNR: 59.7/59.7 dB (typ)SFDR: 71.2/72 dBc (typ)Power per Channel: 1.25/1.01 W (typ)

All trademarks are the property of their respective owners.

  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 1.6/1.0 GSPS Interleaved or 800/500 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 1.6/1.0 GSPS ADCIMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61 dBc (typ)IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69 dBc (typ)Noise Floor: -152.2/-150.5 dBm/Hz (typ)Noise Power Ratio: 50.4/50.7 dB (typ)Power: 2.50/2.02 W (typ)
    • Dual 800/500 MSPS ADC, Fin = 498 MHzENOB: 9.5/9.6 Bits (typ)SNR: 59.7/59.7 dB (typ)SFDR: 71.2/72 dBc (typ)Power per Channel: 1.25/1.01 W (typ)

All trademarks are the property of their respective owners.

The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 7th Nyquist zone

The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 7th Nyquist zone

The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC 數(shù)據(jù)表 (Rev. E) 2013年 3月 25日
應(yīng)用手冊 AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 2017年 2月 3日
應(yīng)用手冊 Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs 2014年 8月 6日
應(yīng)用手冊 Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 2013年 12月 9日
用戶指南 Schematic and Layout Recommendations for the GSPS ADC 2013年 4月 29日
應(yīng)用手冊 AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 2013年 4月 26日
應(yīng)用手冊 From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 2012年 12月 18日
產(chǎn)品概述 ADC12Dxx00RF Direct RF-Sampling ADC Family 2012年 5月 16日
設(shè)計(jì)指南 適用于 Xilinx FPGA 的模擬器件 解決方案指南 2012年 4月 24日

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WAVEVISION5 — WaveVision 5 Software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

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支持的產(chǎn)品和硬件

產(chǎn)品
高速 ADC (≥10 MSPS)
ADC08D1020 — 8 位、雙路 1.0GSPS 或單路 2.0GSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC08D1520 — 8 位、雙通道 1.5GSPS 或單通道 3.0GSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC10D1000 — 10 位、雙通道 1.0GSPS 或單通道 2.0GSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC10D1500 — 10 位、雙通道 1.5GSPS 或單通道 3.0GSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC10DV200 — 雙通道、10 位、200MSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC12D1000 — 12 位、雙通道 1.0GSPS 或單通道 2.0GSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC12D1000RF — 12 位、雙通道 1.0GSPS 或單通道 2.0GSPS 射頻采樣模數(shù)轉(zhuǎn)換器 (ADC) ADC12D1600 — 12 位、雙通道 1.6GSPS 或單通道 3.2GSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC12D1600RF — 12 位雙通道 1.6GSPS 或單通道 3.2GSPS 射頻采樣模數(shù)轉(zhuǎn)換器 (ADC) ADC12D1800 — 12 位、雙通道 1.8GSPS 或單通道 3.6GSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC12D1800RF — 12 位、雙通道 1.8GSPS 或單通道 3.6GSPS、射頻采樣模數(shù)轉(zhuǎn)換器 (ADC) ADC12D500RF — 12 位、雙通道 500MSPS 或單通道 1.0GSPS 射頻采樣模數(shù)轉(zhuǎn)換器 (ADC) ADC12D800RF — 12 位、雙通道 800MSPS 或單通道 1.6GSPS 射頻采樣模數(shù)轉(zhuǎn)換器 (ADC) ADC14DC080 — 雙通道、14 位、80MSPS、1.0GHz 輸入帶寬模數(shù)轉(zhuǎn)換器 (ADC) ADC16DV160 — 雙通道、16 位、160MSPS 模數(shù)轉(zhuǎn)換器 (ADC) ADC16V130 — 16 位、130MSPS 模數(shù)轉(zhuǎn)換器 (ADC)
硬件開發(fā)
評估板
ADC12D1600RB — 12 位雙路 1.6/1.8 GSPS 或單路 3.2/3.6 GSPS A/D 轉(zhuǎn)換器參考板 LM98640CVAL — 具有 LVDS 輸出的雙通道、14 位、40 MSPS 模擬前端 WAVEVSN-BRD-5.1 — WaveVision 5 數(shù)據(jù)捕獲板（5.1 版）
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WAVEVISION5 — Data Acquisition and Analysis Software
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ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS Model
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參考設(shè)計(jì)

TIDA-00113 — 在單通道模式或雙通道模式下針對高帶寬應(yīng)用驅(qū)動 GSPS ADC

該設(shè)計(jì)旨在幫助系統(tǒng)設(shè)計(jì)人員權(quán)衡利弊，推動具有每秒千兆取樣率的 ADC（采用平衡-非平衡變壓器配置）在帶寬應(yīng)用中的應(yīng)用，并對該實(shí)施過程進(jìn)行優(yōu)化。需考慮的權(quán)衡因素包括平衡-非平衡變壓器的結(jié)構(gòu)、插入損耗、動態(tài)性能、可配置性和實(shí)施的簡便性。拓?fù)浜筒季衷趦?yōu)化系統(tǒng)性能的過程中尤為重要，這也正是這些設(shè)計(jì)能夠有助于縮短設(shè)計(jì)周期的原因所在。
設(shè)計(jì)指南: PDF
原理圖: PDF
參考設(shè)計(jì)

TIDA-00479 — GSPS ADC 的最理想時(shí)鐘源參考設(shè)計(jì)

ADC12D1600RFRB 參考設(shè)計(jì)提供了展示高速數(shù)字轉(zhuǎn)換器應(yīng)用（其中整合了時(shí)鐘、電源管理和信號處理）的平臺。此參考設(shè)計(jì)利用 1.6 GSPS ADC12D1600RF 器件、板載 FPGA Xilinx Virtex 4 和高性能時(shí)鐘合成器 LMX2531 來滿足 9 位 ENOB 高速數(shù)字轉(zhuǎn)換器的系統(tǒng)要求。
設(shè)計(jì)指南: PDF
原理圖: PDF
參考設(shè)計(jì)

TIDA-00071 — 每秒千兆次采樣 (GSPS) ADC 的原理圖和布局建議

此參考設(shè)計(jì)為系統(tǒng)中采用 GSPS ADC 的系統(tǒng)設(shè)計(jì)人員提供了原理圖和布局參考。將此參考設(shè)計(jì)與數(shù)據(jù)表結(jié)合使用 — 數(shù)據(jù)表始終具有最終權(quán)威性。另外， ADC1xDxxxx(RF)RB 參考板提供有用的參考設(shè)計(jì)。產(chǎn)品網(wǎng)頁上或“TI 設(shè)計(jì)”中提供了此參考板的所有設(shè)計(jì)源文件以及用于 ADC 的 CAD/CAE 符號，可進(jìn)行下載。在本文檔中，ADC 或 GSPS ADC 指代 (...)
用戶指南: PDF
原理圖: PDF
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PBGA (NXA) 292 Ultra Librarian

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包含信息：
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  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
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