SLUSFS4A September 2025 – September 2025 UCC27734-Q1 , UCC27735-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Input Stages and Interlock
- 6.3.2 Enable Function (UCC277x5-Q1 Only)
- 6.3.3 Undervoltage Lockout (UVLO)
- 6.3.4 Level Shifter
- 6.3.5 Output Stage
- 6.3.6 Low Propagation Delays and Tightly Matched Outputs
- 6.3.7 HS Node dV/dt
- 6.3.8 Split Grounds (COM and VSS)
- 6.3.9 Operation Under Negative HS Voltage Condition
- 6.4 Device Functional Modes
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Application
- 7.2.1 Design Requirements
- 7.2.2
Detailed Design Procedure
- 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
- 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
- 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
- 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
- 7.2.2.5 Selecting Gate Resistor RHO/RLO
- 7.2.2.6 Selecting Bootstrap Diode
- 7.2.2.7 Estimate the UCC2773x-Q1 Power Losses
- 7.2.2.8 Application Example Schematic Note
- 7.2.3 Application Curves
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- D|14
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
4 Pin Configuration and Functions
Figure 4-1 D Package 14-Pin SOIC Top View
Figure 4-2 D Package 8-Pin SOIC Top ViewTable 4-1 Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | 14D | 8D | ||
| HB | 13 | 8 | I | High-side floating supply. Bypass this pin to HS with a suitable capacitor to sustain boot-strap circuit operation in the desired application, typically 10× bigger than gate capacitance. |
| HI | 1 | 1 | I | Logic input for high-side driver. If HI is unbiased or floating, HO is held low. |
| EN/NC | 4 | – | I | Enable input for high-side and low-side driver. This pin biased low, disables both HO and LO regardless of HI and LI state, This pin biased high or floating enables both HO and LO. |
| HO | 12 | 7 | O | High-side driver output. |
| HS | 11 | 6 | – | Return for high-side floating supply. |
| LI | 2 | 2 | I | Logic input for low-side driver. If LI is unbiased or floating, LO is held low. |
| LO | 6 | 4 | O | Low-side driver output. |
| NC | 8, 9, 10, 14 | – | – | No connection. |
| VDD | 7 | 5 | I | Bias supply input. Power supply for the input logic side of the device and also low-side driver output. Bypass this pin to VSS with typical 1μF SMD capacitor (typically CVDD needs to be 10 × CBOOT). If shunt resistor used between COM and VSS, then also bypass this pin to COM with a 100nF SMD capacitor |
| COM | 5 | 3 | – | Return for low-side driver output. Internally tied to VSS in UCC27734-Q1. |
| VSS | 3 | – | – | Logic ground. |