SLUSFS4A September 2025 – September 2025 UCC27734-Q1 , UCC27735-Q1
PRODUCTION DATA
The level shift circuit (refer to the functional block diagram in Section 6.2) is the interface from the low-voltage input stage to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver. The delay matching of the UCC2773x-Q1 is summarized in Figure 5-5 and Figure 5-4 .