ZHCUAU5A March 2023 – May 2025 AM68 , AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VP-Q1 , TDA4VPE-Q1 , TPS6594-Q1
進入 LP_STANDBY 硬件狀態(tài)就和進入待機狀態(tài)一樣。退出 LP_STANDBY 狀態(tài)會有所不同，需要在進入 LP_STANDBY 狀態(tài)之前完成不同的初始化。另外，當(dāng) PMIC 從 LP_STANDBY 狀態(tài)返回時，PFSM 觸發(fā)條件會由 ENABLE_INT 選通，而在待機狀態(tài)下，觸發(fā)條件由 GPIO 中斷選通。
Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1
Write 0x48:0x7D:0xC0:0x3F // Mask NSLEEP bits
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger TO_STANDBY sequence
After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state
Write 0x48:0x7D:0x00:0x3F // unmask NSLEEP bits
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x65:0x02:0xFD // clear ENABLE_INT