SBASAZ5A October 2024 – September 2025 AMC0386-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety-Related Certifications
- 6.8 Safety Limiting Values
- 6.9 Electrical Characteristics
- 6.10 Switching Characteristics
- 6.11 Timing Diagrams
- 6.12 Insulation Characteristics Curves
- 6.13 Typical Characteristics
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- DFX|15
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.2 Modulator
Figure 7-2 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the AMC0386-Q1. The output V5 of the 1-bit, digital-to-analog converter (DAC) is subtracted from the input voltage VIN = (VSNSP – VSNSN). This subtraction provides an analog voltage V1 at the input of the first integrator stage. The output of the first integrator feeds the input of the second integrator stage. The result of the second integration is an output voltage V3 that is summed with VIN and the V2 output. VIN is the input signal and V2 is the first integrator. Depending on the value of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse by changing the associated analog output voltage V5. Thus, causing the integrators to progress in the opposite direction and forcing the integrator output value to track the average value of the input.
Figure 7-2 Block Diagram of the
Second-Order Modulator