SBASAZ5A October 2024 – September 2025 AMC0386-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Ratings
- 6.6 Insulation Specifications
- 6.7 Safety-Related Certifications
- 6.8 Safety Limiting Values
- 6.9 Electrical Characteristics
- 6.10 Switching Characteristics
- 6.11 Timing Diagrams
- 6.12 Insulation Characteristics Curves
- 6.13 Typical Characteristics
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DFX|15
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
7.3.4.1 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC0386-Q1, the device generates a single one or zero every 128 bits at DOUT. Figure 7-5 shows a timing diagram of this process. A single 1 or 0 is generated depending on the actual polarity of the signal being sensed. A full-scale signal is defined as |VSNSP – VSNSN| ≥ |VClipping|. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the system level. See the Diagnosing Delta-Sigma Modulator Bitstream Using C2000? Configurable Logic Block (CLB) application note for code examples of diagnosing the digital bitstream.
Figure 7-5 Full-Scale
Output of the AMC0386-Q1