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SBASAZ5A October 2024 – September 2025 AMC0386-Q1

PRODUCTION DATA

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DFX|15

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6.9 Electrical Characteristics

minimum and maximum specifications apply from T_A = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, V_SNSP = –1 V to +1 V, and V_SNSN = 0V; typical specifications are at T_A = 25°C, AVDD = 5 V, DVDD = 3.3 V, and f_CLKIN = 10 MHz (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
R_IN	Input resistance	AMC0386M06-Q1		10		M?
R_IN	Input resistance	AMC0386M10-Q1		12.5		M?
	Nominal resistive divider ratio	V_HVIN / V_SNSP, AMC0386M06-Q1	598	601	604
	Nominal resistive divider ratio	V_HVIN / V_SNSP, AMC0386M10-Q1	997	1001	1005
CMTI	Common-mode transient immunity		150			V/ns
DC ACCURACY
E_O	Input offset error	Referred to SNSP, T_A = 25°C, HVIN = AGND	–0.9	±0.08	0.9	mV
		Referred to HVIN, T_A = 25°C, HVIN = AGND AMC0386M06-Q1	–540	±50	540
		Referred to HVIN, T_A = 25°C, HVIN = AGND AMC0386M10-Q1	–900	±80	900
TCE_O	Offset error temperature drift⁽³⁾	Referred to SNSP, T_A = 25°C, HVIN = AGND		0.0035	0.007	mV/°C
		Referred to HVIN, HVIN = AGND AMC0386M06-Q1		2.1	4.2
		Referred to HVIN, HVIN = AGND AMC0386M10-Q1		3.5	7
E_A	Attenuation error⁽¹⁾⁽⁶⁾	T_A = 25°C	–0.25	±0.02	0.25	%
TCE_A	Attenuation error temperature drift⁽⁴⁾		–30	±8	30	ppm/°C
INL	Integral nonlinearity⁽²⁾	Resolution: 16 bits	–9	±1.9	9	LSB
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
PSRR	Power-supply rejection ratio⁽⁵⁾	AVDD DC PSRR, HVIN = AGND, AVDD from 3.0V to 5.5V		–83		dB
PSRR	Power-supply rejection ratio⁽⁵⁾	AVDD AC PSRR, HVIN = AGND, AVDD with 10kHz / 100mV ripple		–54		dB
AC ACCURACY
SNR	Signal-to-noise ratio	V_SNSP = 2V_PP, SNSN = AGND, f_IN = 1kHz	84.5	89		dB
SINAD	Signal-to-noise + distortion	V_SNSP = 2V_PP, SNSN = AGND, f_IN = 1kHz	76	84		dB
THD	Total harmonic distortion	V_SNSP = 2V_PP, SNSN = AGND, f_IN = 1kHz		–88	–77	dB
DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)
I_IN	Input current	DGND ≤ V_IN ≤ DVDD			7	μA
C_IN	Input capacitance			4		pF
V_IH	High-level input voltage		0.7 x DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 x DVDD	V
DIGITAL OUTPUT (CMOS)
C_LOAD	Output load capacitance	f_CLKIN = 10MHz		15	30	pF
V_OH	High-level output voltage	I_OH = –4mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 4mA			0.4	V
POWER SUPPLY
I_AVDD	High-side supply current			5.3	7	mA
I_DVDD	Low-side supply current	C_LOAD = 15pF		3.6	5	mA
AVDD_UV	High-side undervoltage detection threshold	AVDD rising,	2.4	2.6	2.8	V
AVDD_UV	High-side undervoltage detection threshold	AVDD falling,	1.9	2.05	2.2	V
DVDD_UV	Low-side undervoltage detection threshold	DVDD rising	2.3	2.5	2.7	V
DVDD_UV	Low-side undervoltage detection threshold	DVDD falling,	1.9	2.05	2.2	V

(1) The typical value includes one sigma statistical variation.

(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(3) Offset error drift is calculated using the box method, as described by the following equation:
TCE_O = (value_MAX - value_MIN) / TempRange

(4) Attenuation error drift is calculated using the box method, as described by the following equation:
TCE_A (ppm) = ((value_MAX - value_MIN) / (value x TempRange)) X 10⁶

(5) This parameter is referred to SNSP.

(6) Includes any error from the resistive divider at the input.