SBASAZ5A October 2024 – September 2025 AMC0386-Q1
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
If the high-side supply (AVDD) is missing, the device provides a constant bitstream of logic 0's at the output, and DOUT is permanently low. Figure 7-6 shows a timing diagram of this process. A one is not generated every 128 clock pulses, which differentiates this condition from a valid negative fullscale input. This feature helps identify high-side power-supply problems on the board. See the Diagnosing Delta-Sigma Modulator Bitstream Using C2000? Configurable Logic Block (CLB) application note for code examples of diagnosing the digital bitstream.